New upstream version 3.3.8

parent cf360915
:[diStorm4}:
:[diStorm3}:
The ultimate disassembler library.
Copyright (c) 2003-2016, Gil Dabah
Copyright (c) 2003-2018, Gil Dabah
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement:
This product includes software developed by Gil Dabah.
4. Neither the name of Gil Dabah nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the Gil Dabah nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY Gil Dabah ''AS IS'' AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL Gil Dabah BE LIABLE FOR ANY
DISCLAIMED. IN NO EVENT SHALL GIL DABAH BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
......@@ -4,7 +4,7 @@ setup.py
include\distorm.h
include\mnemonics.h
python\distorm3\__init__.py
python\distorm3\sample.py
examples\python\sample.py
src\config.h
src\decoder.c
src\decoder.h
......@@ -23,3 +23,8 @@ src\textdefs.h
src\wstring.c
src\wstring.h
src\x86defs.h
make\win32\cdistorm.vcxproj
make\win32\cdistorm.vcxproj.filters
make\win32\distorm.sln
make\win32\resource.h
make\win32\Resource.rc
include COPYING setup.cfg setup.py
include make\win32\cdistorm.vcxproj make\win32\cdistorm.vcxproj.filters make\win32\distorm.sln make\win32\resource.h make\win32\Resource.rc
recursive-include src *.c *.h
recursive-include include *.c *.h
recursive-include . *.py
\ No newline at end of file
recursive-include . *.py
......@@ -9,4 +9,11 @@ diStorm3 is super lightweight (~45KB), ultra fast and easy to use (a single API)
"We benchmarked five popular open-source disassembly libraries and chose diStorm3, which had the best performance (and furthermore, has complete 64-bit support).", July 2014, Quoting David Williams-King in his Thesis about Binary Shuffling.
diStorm3.3.3 is now licensed under BSD!
\ No newline at end of file
diStorm3 is licensed under BSD!
Installing diStorm3 -
Clone repo locally and then 'python setup.py install' or alternatively: 'python -m pip install distorm3'.
For Windows, use these pre-built installers in https://pypi.org/manage/project/distorm3/release/3.3.8/.
RTFM, the wiki has plenty of info.
This diff is collapsed.
# All VIAL and diStorm3 code are based on the order of this list, do NOT edit!
REGISTERS = [
"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", "XX",
"EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI", "R8D", "R9D", "R10D", "R11D", "R12D", "R13D", "R14D", "R15D", "XX",
"AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "R8W", "R9W", "R10W", "R11W", "R12W", "R13W", "R14W", "R15W", "XX",
"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8B", "R9B", "R10B", "R11B", "R12B", "R13B", "R14B", "R15B", "XX",
"SPL", "BPL", "SIL", "DIL", "XX",
"ES", "CS", "SS", "DS", "FS", "GS", "XX",
"RIP", "XX",
"ST0", "ST1", "ST2", "ST3", "ST4", "ST5", "ST6", "ST7", "XX",
"MM0", "MM1", "MM2", "MM3", "MM4", "MM5", "MM6", "MM7", "XX",
"XMM0", "XMM1", "XMM2", "XMM3", "XMM4", "XMM5", "XMM6", "XMM7", "XMM8", "XMM9", "XMM10", "XMM11", "XMM12", "XMM13", "XMM14", "XMM15", "XX",
"YMM0", "YMM1", "YMM2", "YMM3", "YMM4", "YMM5", "YMM6", "YMM7", "YMM8", "YMM9", "YMM10", "YMM11", "YMM12", "YMM13", "YMM14", "YMM15", "XX",
"CR0", "", "CR2", "CR3", "CR4", "", "", "", "CR8", "XX",
"DR0", "DR1", "DR2", "DR3", "", "", "DR6", "DR7"]
regsText = "const _WRegister _REGISTERS[] = {\n\t"
regsEnum = "typedef enum {\n\t"
old = "*"
unused = 0
for i in REGISTERS:
if old != "*":
if old == "XX":
regsText += "\n\t"
regsEnum += "\n\t"
old = i
continue
else:
regsText += "{%d, \"%s\"}," % (len(old), old)
if len(old):
regsEnum += "R_%s," % old
else:
regsEnum += "R_UNUSED%d," % unused
unused += 1
if i != "XX":
regsText += " "
regsEnum += " "
old = i
regsText += "{%d, \"%s\"}\n};\n" % (len(old), old)
regsEnum += "R_" + old + "\n} _RegisterType;\n"
print(regsEnum)
print(regsText)
\ No newline at end of file
......@@ -66,7 +66,7 @@ class InstructionInfo:
if isModRMIncluded:
self.flags |= InstFlag.MODRM_INCLUDED
# Does it use any of the VEX.vvvv field to describe an operand?
if len(filter(lambda x: x in [OperandType.VXMM, OperandType.VYMM, OperandType.VYXMM], self.operands)) == 0:
if len(list(filter(lambda x: x in [OperandType.VXMM, OperandType.VYMM, OperandType.VYXMM], self.operands))) == 0:
self.flags |= InstFlag.VEX_V_UNUSED
self.VEXtag = ""
# Special treatment for VEX instructions:
......@@ -122,7 +122,7 @@ class InstructionsTable:
self.__iterIndex = -1
return self
def next(self):
def __next__(self):
""" This is the core of the iterator, return the next instruction or halt. """
# Get next instruction.
self.__iterIndex += 1
......@@ -136,12 +136,15 @@ class InstructionsTable:
raise StopIteration
# If we have the key return its corresponding opcode,
# it might be that we return an object of another nested InstructionTable as well.
if self.list.has_key(self.__iterIndex):
if self.__iterIndex in self.list:
item = self.list[self.__iterIndex]
return item
# In case no InstructionInfo or InstructionsTable were found, return None (this doesn't stop the iteration!).
return None
# Fix for Python2.x
next = __next__
class GenBlock:
""" There are some special instructions which have the operand encoded in the code byte itself.
For instance: 40: INC EAX 41: ECX. push/pop/dec, etc...
......@@ -171,7 +174,7 @@ class GenBlock:
self.list.__iter__()
return self
def next(self):
def __next__(self):
# Get next item from internal iterator.
i = self.list.next()
# If there's an item set, it means we hit the special opcode before.
......@@ -195,6 +198,9 @@ class GenBlock:
# Return the instruction we read from the real list.
return i
# Fix for Python2.x
next = __next__
class InstructionsDB:
""" The Instructions Data Base holds all instructions under it.
The self.root is where all instructions begin, so instructions that are 1 byte long, will be set directly there.
......@@ -216,12 +222,12 @@ class InstructionsDB:
if ii.flags & InstFlag.PRE_VEX:
ii.tag = "_%s%s" % (ii.VEXtag, ii.tag)
# If there is nothing at this index, create a prefixed table.
if o.list.has_key(pos[0]) == False:
if pos[0] not in o.list:
o.list[pos[0]] = InstructionsTable(InstructionsTable.Prefixed, tag, "")
# If there's a table constructred already (doesn't matter if by last line).
if isinstance(o.list[pos[0]], InstructionsTable) and o.list[pos[0]].type == NodeType.LIST_PREFIXED:
# Check for obvious collision.
if o.list[pos[0]].list.has_key(ii.entryNo):
if ii.entryNo in o.list[pos[0]].list:
raise DBException("Collision in prefix table.")
# Link the instruction to its index.
o.list[pos[0]].list[ii.entryNo] = ii
......@@ -311,7 +317,7 @@ class InstructionsDB:
if ii.prefixed:
self.HandleMandatoryPrefix(type, o, pos, ii, tag)
return
if o.list.has_key(pos[0]) == True:
if pos[0] in o.list:
self.HandleMandatoryPrefix(type, o, pos, ii, tag)
return
# Link the instruction info in its place.
......@@ -319,7 +325,7 @@ class InstructionsDB:
# Stop recursion.
return
# See whether we have to create a nested table.
if o.list.has_key(pos[0]) == False:
if pos[0] not in o.list:
# All tables are full sized.
tableType = InstructionsTable.Full
if type == OpcodeLength.OL_13:
......
This diff is collapsed.
......@@ -178,7 +178,7 @@ class InstFlag:
VEX_V_UNUSED, # 38
GEN_BLOCK, # 39 From here on: internal to disOps.
EXPORTED # 40
) = [1 << i for i in xrange(41)]
) = [1 << i for i in range(41)]
# Nodes are extended if they have any of the following flags:
EXTENDED = (PRE_VEX | USE_EXMNEMONIC | USE_EXMNEMONIC2 | USE_OP3 | USE_OP4)
SEGMENTS = (PRE_CS | PRE_SS | PRE_DS | PRE_ES | PRE_FS | PRE_FS)
......@@ -244,4 +244,4 @@ class CPUFlags:
OF, # 5
ZF, # 6
SF # 7
) = [1 << i for i in xrange(8)]
) = [1 << i for i in range(8)]
......@@ -117,8 +117,8 @@ class Instructions:
Set("0f, ad", ["SHRD"], [OPT.RM_FULL, OPT.REG_FULL, OPT.REGCL], IFlag.MODRM_REQUIRED | IFlag._32BITS)
Set("0f, ae /00", ["FXSAVE", "", "FXSAVE64"], [OPT.MEM], IFlag.MODRM_REQUIRED | IFlag._32BITS | IFlag._64BITS | IFlag.PRE_REX | IFlag.USE_EXMNEMONIC2)
Set("0f, ae /01", ["FXRSTOR", "", "FXRSTOR64"], [OPT.MEM], IFlag.MODRM_REQUIRED | IFlag._32BITS | IFlag._64BITS | IFlag.PRE_REX | IFlag.USE_EXMNEMONIC2)
Set("0f, ae /02", ["LDMXCSR"], [OPT.MEM], IFlag.MODRM_REQUIRED | IFlag._32BITS)
Set("0f, ae /03", ["STMXCSR"], [OPT.MEM], IFlag.MODRM_REQUIRED | IFlag._32BITS)
Set("0f, ae /02", ["LDMXCSR"], [OPT.MEM32], IFlag.MODRM_REQUIRED | IFlag._32BITS)
Set("0f, ae /03", ["STMXCSR"], [OPT.MEM32], IFlag.MODRM_REQUIRED | IFlag._32BITS)
# MFENCE and XSAVEOPT share the same opcode 0f ae /6. It's MFENCE when MOD=11, else XSAVEOPT or XSAVEOPT64 in 64.
Set("0f, ae /06", ["MFENCE", "XSAVEOPT", "XSAVEOPT64"], [OPT.MEM_OPT], IFlag.MODRM_REQUIRED | IFlag._32BITS | IFlag.USE_EXMNEMONIC | IFlag.MNEMONIC_MODRM_BASED | IFlag._64BITS | IFlag.PRE_REX | IFlag.USE_EXMNEMONIC2)
......
......@@ -38,19 +38,31 @@ def Assemble(text, mode):
if mode is None:
mode = 32
lines = ("bits %d\r\n" % mode) + lines
open("1.asm", "wb").write(lines)
open("1.asm", "wb").write(lines.encode())
if mode == 64:
mode = "amd64"
else:
mode = "x86"
os.system("yasm.exe -m%s 1.asm" % mode)
return open("1", "rb").read()
os.system("c:\\yasm -m%s 1.asm" % mode)
s = open("1", "rb").read()
#if (not isinstance(s, str)):
return s
class InstBin(unittest.TestCase):
class Test(unittest.TestCase):
def __init__(self):
unittest.TestCase.__init__(self, "test_dummy")
def test_dummy(self):
self.fail("dummy")
class InstBin(Test):
def __init__(self, bin, mode):
bin = bin.decode("hex")
Test.__init__(self)
try:
bin = bin.decode("hex")
except:
bin = bytes.fromhex(bin)
#fbin[mode].write(bin)
self.insts = Decompose(0, bin, mode)
self.insts = Decompose(0, bin, mode)
self.inst = self.insts[0]
def check_valid(self, instsNo = 1):
self.assertNotEqual(self.inst.rawFlags, 65535)
......@@ -61,8 +73,9 @@ class InstBin(unittest.TestCase):
self.assertNotEqual(self.inst.rawFlags, 65535)
self.assertEqual(self.insts[instNo].mnemonic, mnemonic)
class Inst(unittest.TestCase):
class Inst(Test):
def __init__(self, instText, mode, instNo, features):
Test.__init__(self)
modeSize = [16, 32, 64][mode]
bin = Assemble(instText, modeSize)
#print map(lambda x: hex(ord(x)), bin)
......@@ -311,12 +324,12 @@ class TestMode16(unittest.TestCase):
I16("fxch st4").check_reg(0, Regs.ST4, 32)
def test_fpu_ssi(self):
a = I16("fcmovnbe st0, st3")
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
def test_fpu_sis(self):
a = I16("fadd st3, st0")
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
def test_mm(self):
I16("pand mm0, mm7").check_reg(0, Regs.MM0, 64)
def test_mm_rm(self):
......@@ -540,12 +553,12 @@ class TestMode32(unittest.TestCase):
I32("fxch st4").check_reg(0, Regs.ST4, 32)
def test_fpu_ssi(self):
a = I32("fcmovnbe st0, st3")
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
def test_fpu_sis(self):
a = I32("fadd st3, st0")
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
def test_mm(self):
I32("pand mm0, mm7").check_reg(0, Regs.MM0, 64)
def test_mm_rm(self):
......@@ -840,12 +853,12 @@ class TestMode64(unittest.TestCase):
I64("fxch st4").check_reg(0, Regs.ST4, 32)
def test_fpu_ssi(self):
a = I64("fcmovnbe st0, st3")
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
a.check_reg(0, Regs.ST0, 32)
a.check_reg(1, Regs.ST3, 32)
def test_fpu_sis(self):
a = I64("fadd st3, st0")
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
a.check_reg(0, Regs.ST3, 32)
a.check_reg(1, Regs.ST0, 32)
def test_mm(self):
I64("pand mm0, mm7").check_reg(0, Regs.MM0, 64)
def test_mm_rm(self):
......@@ -996,7 +1009,7 @@ class TestInstTable(unittest.TestCase):
IB64("c6f8bb").check_mnemonic("XABORT")
IB64("c7f800000000").check_mnemonic("XBEGIN")
def test_fuzz_9b_and_c7(self):
for i in xrange(10000):
for i in range(10000):
s = "%02x%02x" % (i & 0xff, random.randint(0, 255))
IB32("9b%sffffffff" % s)
IB32("c7%sffffffff" % s)
......@@ -1582,7 +1595,7 @@ class TestPrefixes(unittest.TestCase):
class TestInvalid(unittest.TestCase):
def align(self):
for i in xrange(15):
for i in range(15):
IB32("90")
def test_filter_mem(self):
#cmpxchg8b eax
......
......@@ -6,7 +6,7 @@ distorm.h
diStorm3 - Powerful disassembler for X86/AMD64
http://ragestorm.net/distorm/
distorm at gmail dot com
Copyright (C) 2003-2016 Gil Dabah
Copyright (C) 2003-2018 Gil Dabah
This library is licensed under the BSD license. See the file COPYING.
*/
......
This diff is collapsed.
......@@ -5,7 +5,15 @@
TARGET = libdistorm3.so
COBJS = ../../src/mnemonics.o ../../src/wstring.o ../../src/textdefs.o ../../src/prefix.o ../../src/operands.o ../../src/insts.o ../../src/instructions.o ../../src/distorm.o ../../src/decoder.o
CC = gcc
CFLAGS = -fPIC -O2 -Wall -DSUPPORT_64BIT_OFFSET -DDISTORM_STATIC
CFLAGS += -fPIC -O2 -Wall -DSUPPORT_64BIT_OFFSET -DDISTORM_STATIC
LDFLAGS += -shared
PREFIX = /usr/local
# The lib SONAME version:
LIB_S_VERSION = 3
# The lib real version:
LIB_R_VERSION = 3.3.8
LDFLAGS += -Wl,-soname,${TARGET}.${LIB_S_VERSION}
DESTDIR =
all: clib
......@@ -13,11 +21,11 @@ clean:
/bin/rm -rf ../../src/*.o ${TARGET} ../../distorm3.a ./../*.o
clib: ${COBJS}
${CC} ${CFLAGS} ${VERSION} ${COBJS} -shared -o ${TARGET}
${CC} ${CFLAGS} ${VERSION} ${COBJS} ${LDFLAGS} -o ${TARGET}
ar rs ../../distorm3.a ${COBJS}
install: libdistorm3.so
install -s ${TARGET} /usr/local/lib
install -D -s ${TARGET} ${DESTDIR}/${PREFIX}/lib/${TARGET}
@echo "... running ldconfig might be smart ..."
.c.o:
......
<?xml version="1.0" encoding="utf-8"?>
<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<Project DefaultTargets="Build" ToolsVersion="15.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
<ItemGroup Label="ProjectConfigurations">
<ProjectConfiguration Include="clib|Win32">
<Configuration>clib</Configuration>
......@@ -23,6 +23,7 @@
<ProjectGuid>{15051CE1-AB10-4239-973D-01B84F2AD0A9}</ProjectGuid>
<RootNamespace>distorm</RootNamespace>
<Keyword>Win32Proj</Keyword>
<WindowsTargetPlatformVersion>10.0.17134.0</WindowsTargetPlatformVersion>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='dll|Win32'" Label="Configuration">
......@@ -30,22 +31,26 @@
<UseOfAtl>false</UseOfAtl>
<CharacterSet>NotSet</CharacterSet>
<UseOfMfc>false</UseOfMfc>
<PlatformToolset>v141</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='clib|Win32'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<UseOfAtl>false</UseOfAtl>
<CharacterSet>MultiByte</CharacterSet>
<CharacterSet>NotSet</CharacterSet>
<PlatformToolset>v141</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='dll|x64'" Label="Configuration">
<ConfigurationType>DynamicLibrary</ConfigurationType>
<UseOfAtl>false</UseOfAtl>
<CharacterSet>NotSet</CharacterSet>
<UseOfMfc>false</UseOfMfc>
<PlatformToolset>v141</PlatformToolset>
</PropertyGroup>
<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='clib|x64'" Label="Configuration">
<ConfigurationType>StaticLibrary</ConfigurationType>
<UseOfAtl>false</UseOfAtl>
<CharacterSet>MultiByte</CharacterSet>
<CharacterSet>NotSet</CharacterSet>
<PlatformToolset>v141</PlatformToolset>
</PropertyGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
<ImportGroup Label="ExtensionSettings">
......@@ -114,6 +119,7 @@
<CompileAs>CompileAsC</CompileAs>
<ProgramDataBaseFileName>distorm.pdb</ProgramDataBaseFileName>
<WarningLevel>Level4</WarningLevel>
<TreatWarningAsError>true</TreatWarningAsError>
</ClCompile>
<Lib>
<TargetMachine>MachineX86</TargetMachine>
......@@ -132,7 +138,7 @@
<AdditionalIncludeDirectories>%(AdditionalIncludeDirectories)</AdditionalIncludeDirectories>
<PreprocessorDefinitions>WIN32;NDEBUG;DISTORM_STATIC;SUPPORT_64BIT_OFFSET;%(PreprocessorDefinitions)</PreprocessorDefinitions>
<StringPooling>true</StringPooling>
<MinimalRebuild>false</MinimalRebuild>
<MinimalRebuild>true</MinimalRebuild>
<ExceptionHandling>false</ExceptionHandling>
<RuntimeLibrary>MultiThreaded</RuntimeLibrary>
<FunctionLevelLinking>true</FunctionLevelLinking>
......@@ -140,8 +146,7 @@
</PrecompiledHeader>
<WarningLevel>Level4</WarningLevel>
<TreatWarningAsError>true</TreatWarningAsError>
<DebugInformationFormat>
</DebugInformationFormat>
<DebugInformationFormat>ProgramDatabase</DebugInformationFormat>
<CompileAs>CompileAsC</CompileAs>
<ProgramDataBaseFileName>distorm.pdb</ProgramDataBaseFileName>
</ClCompile>
......@@ -169,7 +174,7 @@
<CompileAs>CompileAsC</CompileAs>
<BufferSecurityCheck>true</BufferSecurityCheck>
<ProgramDataBaseFileName>distorm3.pdb</ProgramDataBaseFileName>
<RuntimeLibrary>MultiThreaded</RuntimeLibrary>
<RuntimeLibrary>MultiThreadedDLL</RuntimeLibrary>
</ClCompile>
<Link />
<ProjectReference />
......@@ -190,7 +195,7 @@
<StringPooling>true</StringPooling>
<MinimalRebuild>true</MinimalRebuild>
<ExceptionHandling>false</ExceptionHandling>
<RuntimeLibrary>MultiThreaded</RuntimeLibrary>
<RuntimeLibrary>MultiThreadedDLL</RuntimeLibrary>
<FunctionLevelLinking>true</FunctionLevelLinking>
<PrecompiledHeader>
</PrecompiledHeader>
......@@ -221,6 +226,7 @@
<ItemGroup>
<ClInclude Include="..\..\src\config.h" />
<ClInclude Include="..\..\include\distorm.h" />
<ClInclude Include="..\..\src\decoder.h" />
<ClInclude Include="..\..\src\instructions.h" />
<ClInclude Include="..\..\src\insts.h" />
<ClInclude Include="..\..\include\mnemonics.h" />
......@@ -229,9 +235,10 @@
<ClInclude Include="..\..\src\textdefs.h" />
<ClInclude Include="..\..\src\wstring.h" />
<ClInclude Include="..\..\src\x86defs.h" />
<ClInclude Include="resource.h" />
</ItemGroup>
<ItemGroup>
<ResourceCompile Include="resource.rc" />
<ResourceCompile Include="Resource.rc" />
</ItemGroup>
<Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
<ImportGroup Label="ExtensionTargets">
......
......@@ -38,9 +38,6 @@
<ClCompile Include="..\..\src\wstring.c">
<Filter>Source Files</Filter>
</ClCompile>
<ClCompile Include="..\..\src\x86defs.c">
<Filter>Source Files</Filter>
</ClCompile>
</ItemGroup>
<ItemGroup>
<ClInclude Include="..\..\src\config.h">
......@@ -73,8 +70,14 @@
<ClInclude Include="..\..\src\x86defs.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="resource.h">
<Filter>Header Files</Filter>
</ClInclude>
<ClInclude Include="..\..\src\decoder.h">
<Filter>Header Files</Filter>
</ClInclude>
</ItemGroup>
<ItemGroup>
<ResourceCompile Include="resource.rc" />
<ResourceCompile Include="Resource.rc" />
</ItemGroup>
</Project>
\ No newline at end of file
......@@ -12,3 +12,17 @@
#define _APS_NEXT_SYMED_VALUE 101
#endif
#endif
//{{NO_DEPENDENCIES}}
// Microsoft Visual C++ generated include file.
// Used by Resource.rc
// Next default values for new objects
//
#ifdef APSTUDIO_INVOKED
#ifndef APSTUDIO_READONLY_SYMBOLS
#define _APS_NEXT_RESOURCE_VALUE 101
#define _APS_NEXT_COMMAND_VALUE 40001
#define _APS_NEXT_CONTROL_VALUE 1001
#define _APS_NEXT_SYMED_VALUE 101
#endif
#endif
B// Microsoft Visual C++ generated resource script.
......
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This diff is collapsed.
This diff is collapsed.
......@@ -4,7 +4,7 @@ decoder.c
diStorm3 - Powerful disassembler for X86/AMD64
http://ragestorm.net/distorm/
distorm at gmail dot com
Copyright (C) 2003-2016 Gil Dabah
Copyright (C) 2003-2018 Gil Dabah
This library is licensed under the BSD license. See the file COPYING.
*/
......@@ -91,6 +91,7 @@ static _DecodeResult decode_inst(_CodeInfo* ci, _PrefixState* ps, _DInst* di)
/* Holds the info about the current found instruction. */
_InstInfo* ii = NULL;
_InstInfo iip; /* Privileged instruction cache. */
_InstSharedInfo* isi = NULL;
/* Used only for special CMP instructions which have pseudo opcodes suffix. */
......@@ -111,10 +112,18 @@ static _DecodeResult decode_inst(_CodeInfo* ci, _PrefixState* ps, _DInst* di)
if (ii == NULL) goto _Undecodable;
isi = &InstSharedInfoTable[ii->sharedIndex];
instFlags = FlagsTable[isi->flagsIndex];
/* Copy the privileged bit and remove it from the opcodeId field ASAP. */
privilegedFlag = ii->opcodeId & OPCODE_ID_PRIVILEGED;
ii->opcodeId &= ~OPCODE_ID_PRIVILEGED;
if (privilegedFlag) {
/*
* Copy the privileged instruction info so we can remove the privileged bit
* from the opcodeId field. This makes sure we're not modifying the tables
* in case we lookup this privileged instruction later.
*/
iip = *ii;
iip.opcodeId &= ~OPCODE_ID_PRIVILEGED;
ii = &iip;
}
/*
* If both REX and OpSize are available we will have to disable the OpSize, because REX has precedence.
......
......@@ -5,7 +5,7 @@ diStorm3 C Library Interface
diStorm3 - Powerful disassembler for X86/AMD64
http://ragestorm.net/distorm/
distorm at gmail dot com
Copyright (C) 2003-2016 Gil Dabah
Copyright (C) 2003-2018 Gil Dabah
This library is licensed under the BSD license. See the file COPYING.
*/
......
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......@@ -4,7 +4,7 @@ x86defs.h
diStorm3 - Powerful disassembler for X86/AMD64
http://ragestorm.net/distorm/
distorm at gmail dot com
Copyright (C) 2003-2016 Gil Dabah
Copyright (C) 2003-2018 Gil Dabah
This library is licensed under the BSD license. See the file COPYING.
*/
......
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