Commit e3c0c465 authored by AlexandrX Konovalov's avatar AlexandrX Konovalov Committed by Oleg Nabiullin

Import IPP sources used by MJPEG SW fallback

parent f7145a6b
......@@ -104,6 +104,7 @@ if (BUILD_SAMPLES)
endif()
if (BUILD_RUNTIME)
add_subdirectory(${CMAKE_HOME_DIRECTORY}/contrib/ipp)
add_subdirectory(${CMAKE_HOME_DIRECTORY}/_studio)
endif()
......
# Copyright (c) 2017 Intel Corporation
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in all
# copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
set( MFX_ROOT "${CMAKE_HOME_DIRECTORY}/_studio/shared" )
include_directories (
${CMAKE_CURRENT_SOURCE_DIR}/include
${MFX_ROOT}/include
${MFX_ROOT}/umc/core/umc/include
)
set( SRC_DIR "${CMAKE_CURRENT_SOURCE_DIR}/src" )
# Optimized for processors with Intel SSE4.2
set( defs "-D_Y8 -D_ARCH_EM64T" )
set( sources "" )
file( GLOB_RECURSE srcs "${SRC_DIR}/*.c" "${SRC_DIR}/asm_intel64/*.s" )
list( APPEND sources ${srcs})
enable_language(C ASM)
set( CMAKE_ASM_SOURCE_FILE_EXTENSIONS s )
make_library( ipp none static )
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
#ifndef __CPUDEF_H__
#define __CPUDEF_H__
#include "ippcore.h"
#if defined( __cplusplus )
extern "C" {
#endif
#undef __CDECL
#if defined( _WIN32 ) || defined ( _WIN64 )
#define __CDECL __cdecl
#else
#define __CDECL
#endif
/* Intel CPU informator */
int __CDECL mfxownGetFeature( Ipp64u MaskOfFeature );
int __CDECL mfxhas_cpuid ( void );
int __CDECL mfxis_GenuineIntel ( void );
int __CDECL mfxmax_cpuid_input( void );
#if defined( __cplusplus )
}
#endif
#endif /* __CPUDEF_H__ */
/* ////////////////////////// End of file "cpudef.h" //////////////////////// */
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
#ifndef __DEPENDENCEIP_H__
#define __DEPENDENCEIP_H__
#if (_IPP_ARCH == _IPP_ARCH_XSC)
#ifndef _CORE
#ifndef __IPPI_H__
#include "ippi.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE */
#endif
#endif /* __DEPENDENCEIP_H__ */
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
#ifndef __DEPENDENCESP_H__
#define __DEPENDENCESP_H__
#if (_IPP_ARCH == _IPP_ARCH_XSC)
#ifndef _CORE
#ifndef __IPPS_H__
#include "ipps.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _CORE */
#endif
#endif /* __DEPENDENCESP_H__ */
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
/*
// Intel(R) Integrated Performance Primitives
// Color Conversion Library (ippCC)
//
//
*/
#if !defined( __IPPCC_H__ ) || defined( _OWN_BLDPCS )
#define __IPPCC_H__
#if defined (_WIN32_WCE) && defined (_M_IX86) && defined (__stdcall)
#define _IPP_STDCALL_CDECL
#undef __stdcall
#endif
#ifndef __IPPDEFS_H__
#include "ippdefs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* ////////////////////////////////////////////////////////////////////////////
// Name: mfxiYCbCr422_8u_P3C2R
// Purpose: Converts 422 planar image to YUY2
// Returns:
// ippStsNoErr OK
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr Width of first plain 422-image less than 2(4)
// or height equal zero
//
// Parameters:
// pSrc[3] Array of pointers to the source image planes
// srcStep[3] Array of steps through the source image planes
// pDst[3] Array of pointers to the destination image planes
// dstStep[3] Array of steps through the destination image planes
// pSrc Pointer to the source pixel-order image
// srcStep Step through the source pixel-order image
// pDst Pointer to the destination pixel-order image
// dstStep Step through the destination pixel-order image
// roiSize Size of the ROI
*/
IPPAPI (IppStatus, mfxiYCbCr422_8u_P3C2R, ( const Ipp8u* pSrc[3], int srcStep[3], Ipp8u* pDst, int dstStep, IppiSize roiSize))
IPPAPI(IppStatus, mfxiYCbCr420ToYCbCr422_8u_P2C2R,(const Ipp8u* pSrcY, int srcYStep,const Ipp8u* pSrcCbCr,
int srcCbCrStep, Ipp8u* pDst, int dstStep, IppiSize roiSize))
IPPAPI(IppStatus, mfxiYCrCb420ToYCbCr422_8u_P3C2R,( const Ipp8u* pSrc[3],int srcStep[3], Ipp8u* pDst, int dstStep, IppiSize roiSize ))
/* ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Name: mfxiYCbCr422_8u_C2P3R
// Purpose: Converts a YUY2 image to the P422 image
// Return:
// ippStsNoErr Ok
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr if roiSize.width < 2
//
// Arguments:
// pSrc pointer to the source image
// srcStep step for the source image
// pDst array of pointers to the components of the destination image
// dstStep array of steps values for every component
// roiSize region of interest to be processed, in pixels
// Notes:
// roiSize.width should be multiple 2.
*/
IPPAPI(IppStatus, mfxiYCbCr422_8u_C2P3R,( const Ipp8u* pSrc, int srcStep, Ipp8u* pDst[3],
int dstStep[3], IppiSize roiSize ))
/* ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Name: mfxiYCbCr422ToYCbCr420_8u_C2P3R
// Purpose: Converts a 2-channel YUY2 image to the I420(IYUV) image
// Return:
// ippStsNoErr Ok
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr if roiSize.width < 2 || roiSize.height < 2
//
// Arguments:
// pSrc pointer to the source image
// srcStep step for the source image
// pDst array of pointers to the components of the destination image
// dstStep array of steps values for every component
// roiSize region of interest to be processed, in pixels
// Notes:
// roiSize.width and roiSize.height should be multiple 2.
*/
IPPAPI(IppStatus, mfxiYCbCr422ToYCbCr420_8u_C2P3R,( const Ipp8u* pSrc, int srcStep, Ipp8u* pDst[3],
int dstStep[3], IppiSize roiSize ))
/* ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Name: mfxiYCbCr420_8u_P2P3R
// Purpose: Converts a NV12 image to the I420(IYUV) image.
// Return:
// ippStsNoErr Ok
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr if roiSize.width < 2 || roiSize.height < 2
//
// Arguments:
// pSrcY pointer to the source Y plane
// srcYStep step for the source Y plane
// pSrcCbCr pointer to the source CbCr plane
// srcCbCrStep step for the source CbCr plane
// pDst array of pointers to the components of the destination image
// dstStep array of steps values for every component
// roiSize region of interest to be processed, in pixels
// Notes:
// roiSize.width should be multiple 2.
// roiSize.height should be multiple 2.
*/
IPPAPI(IppStatus, mfxiYCbCr420_8u_P2P3R,(const Ipp8u* pSrcY,int srcYStep,const Ipp8u* pSrcCbCr, int srcCbCrStep,
Ipp8u* pDst[3], int dstStep[3], IppiSize roiSize ))
/* ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Name: mfxiCbYCr422ToYCbCr422_8u_C2P3R
// Purpose: Converts a UYVY image to the P422 image
// Return:
// ippStsNoErr Ok
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr if roiSize.width < 2
//
// Arguments:
// pSrc pointer to the source image
// srcStep step for the source image
// pDst array of pointers to the components of the destination image
// dstStep array of steps values for every component
// roiSize region of interest to be processed, in pixels
// Notes:
// roiSize.width should be multiple 2.
*/
IPPAPI(IppStatus, mfxiCbYCr422ToYCbCr422_8u_C2P3R,( const Ipp8u* pSrc, int srcStep, Ipp8u* pDst[3],
int dstStep[3], IppiSize roiSize ))
/* ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Name: mfxiYCbCr422ToYCbCr420_8u_P3R
// Purpose: Converts a P422 image to the I420(IYUV)image
// Name: mfxiYCbCr420ToYCbCr422_8u_P3R
// Purpose: Converts a IYUV image to the P422 image
// Return:
// ippStsNoErr Ok
// ippStsNullPtrErr One or more pointers are NULL
// ippStsSizeErr if roiSize.width < 2 || roiSize.height < 2
//
// Arguments:
// pSrc array of pointers to the components of the source image
// srcStep array of step values for every component
// pDst array of pointers to the components of the destination image
// dstStep array of steps values for every component
// roiSize region of interest to be processed, in pixels
// Notes:
// roiSize.width and roiSize.height should be multiple 2.
*/
IPPAPI(IppStatus, mfxiYCbCr422ToYCbCr420_8u_P3R,( const Ipp8u* pSrc[3], int srcStep[3], Ipp8u* pDst[3],
int dstStep[3], IppiSize roiSize ))
IPPAPI(IppStatus, mfxiYCbCr420ToYCbCr422_8u_P3R,( const Ipp8u* pSrc[3], int srcStep[3], Ipp8u* pDst[3],
int dstStep[3], IppiSize roiSize ))
#ifdef __cplusplus
}
#endif
#if defined (_IPP_STDCALL_CDECL)
#undef _IPP_STDCALL_CDECL
#define __stdcall __cdecl
#endif
#endif /* __IPPCC_H__ */
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
/*
// Intel(R) Integrated Performance Primitives
// Core (ippCore)
//
//
*/
#if !defined( __IPPCORE_H__ ) || defined( _OWN_BLDPCS )
#define __IPPCORE_H__
#if defined (_WIN32_WCE) && defined (_M_IX86) && defined (__stdcall)
#define _IPP_STDCALL_CDECL
#undef __stdcall
#endif
#ifndef __IPPDEFS_H__
#include "ippdefs.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ippAffinityCompactFineCore, /* KMP_AFFINITY=granularity=fine,compact,n,offset, where n - level */
ippAffinityCompactFineHT, /* KMP_AFFINITY=granularity=fine,compact,0,offset */
ippAffinityAllEnabled, /* KMP_AFFINITY=respect */
ippAffinityRestore,
ippTstAffinityCompactFineCore, /* test mode for affinity type ippAffinityCompactFineCore */
ippTstAffinityCompactFineHT /* test mode for affinity type ippAffinityCompactFineHT */
} IppAffinityType;
/* /////////////////////////////////////////////////////////////////////////////
// Functions to allocate and free memory
///////////////////////////////////////////////////////////////////////////// */
/* /////////////////////////////////////////////////////////////////////////////
// Name: ippMalloc
// Purpose: 64-byte aligned memory allocation
// Parameter:
// len number of bytes
// Returns: pointer to allocated memory
//
// Notes: the memory allocated by ippMalloc has to be free by ippFree
// function only.
*/
IPPAPI( void*, mfxMalloc, (int length) )
/* /////////////////////////////////////////////////////////////////////////////
// Name: ippFree
// Purpose: free memory allocated by the ippMalloc function
// Parameter:
// ptr pointer to the memory allocated by the ippMalloc function
//
// Notes: use the function to free memory allocated by ippMalloc
*/
IPPAPI( void, mfxFree, (void* ptr) )
/* ////////////////////////////////////////////////////////////////////////////
// Name: mfxGetMaxCacheSizeB
//
// Purpose: Detects maximal from the sizes of L2 or L3 in bytes
//
// Return:
// ippStsNullPtrErr The result's pointer is NULL.
// ippStsNotSupportedCpu The cpu is not supported.
// ippStsUnknownCacheSize The cpu is supported, but the size of the cache is unknown.
// ippStsNoErr Ok
//
// Arguments:
// pSizeByte Pointer to the result
//
// Note:
// 1). Intel(R) processors are supported only.
// 2). Intel(R) Itanium(R) processors and platforms with Intel XScale(R) technology are unsupported
// 3). For unsupported processors the result is "0",
// and the return status is "ippStsNotSupportedCpu".
// 4). For supported processors the result is "0",
// and the return status is "ippStsUnknownCacheSize".
// if sizes of the cache is unknown.
//
*/
IPPAPI( IppStatus, mfxGetMaxCacheSizeB, ( int* pSizeByte ) )
#ifdef __cplusplus
}
#endif
#endif /* __IPPCORE_H__ */
// Copyright (c) 2018 Intel Corporation
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
/*
// Intel(R) Integrated Performance Primitives
// Common Types and Macro Definitions
//
//
*/
#ifndef __IPPDEFS_H__
#define __IPPDEFS_H__
#include "umc_defs.h" // for mfxSize
#ifdef __cplusplus
extern "C" {
#endif
#if !defined( IPPAPI )
#if defined( IPP_W32DLL ) && (defined( _WIN32 ) || defined( _WIN64 ))
#if defined( _MSC_VER ) || defined( __ICL )
#define IPPAPI( type,name,arg ) \
__declspec(dllimport) type __STDCALL name arg;
#else
#define IPPAPI( type,name,arg ) type __STDCALL name arg;
#endif
#else
#define IPPAPI( type,name,arg ) type __STDCALL name arg;
#endif
#endif
#define IPP_MAX_8U ( 0xFF )
#define IPP_MIN_16S (-32768 )
#define IPP_MAX_16S ( 32767 )
#define IPP_MAX( a, b ) ( ((a) > (b)) ? (a) : (b) )
#define IPP_MIN( a, b ) ( ((a) < (b)) ? (a) : (b) )
#if !defined( _OWN_BLDPCS )
typedef enum {
/* Enumeration: Processor: */
ippCpuUnknown = 0x00,
ippCpuPP = 0x01, /* Intel(R) Pentium(R) processor */
ippCpuPMX = 0x02, /* Intel(R) Pentium(R) processor with MMX(TM) technology */
ippCpuPPR = 0x03, /* Intel(R) Pentium(R) Pro processor */
ippCpuPII = 0x04, /* Intel(R) Pentium(R) II processor */
ippCpuPIII = 0x05, /* Intel(R) Pentium(R) III processor and Pentium(R) III Xeon(R) processor */
ippCpuP4 = 0x06, /* Intel(R) Pentium(R) 4 processor and Intel(R) Xeon(R) processor */
ippCpuP4HT = 0x07, /* Intel(R) Pentium(R) 4 Processor with HT Technology */
ippCpuP4HT2 = 0x08, /* Intel(R) Pentium(R) 4 processor with Intel(R) Streaming SIMD Extensions 3 */
ippCpuCentrino = 0x09, /* Intel(R) Centrino(R) mobile technology */
ippCpuCoreSolo = 0x0a, /* Intel(R) Core(TM) Solo processor */
ippCpuCoreDuo = 0x0b, /* Intel(R) Core(TM) Duo processor */
ippCpuITP = 0x10, /* Intel(R) Itanium(R) processor */
ippCpuITP2 = 0x11, /* Intel(R) Itanium(R) 2 processor */
ippCpuEM64T = 0x20, /* Intel(R) 64 Instruction Set Architecture (ISA) */
ippCpuC2D = 0x21, /* Intel(R) Core(TM) 2 Duo processor */
ippCpuC2Q = 0x22, /* Intel(R) Core(TM) 2 Quad processor */
ippCpuPenryn = 0x23, /* Intel(R) Core(TM) 2 processor with Intel(R) SSE4.1 */
ippCpuBonnell = 0x24, /* Intel(R) Atom(TM) processor */
ippCpuNehalem = 0x25, /* Intel(R) Core(TM) i7 processor */
ippCpuNext = 0x26,
ippCpuSSE = 0x40, /* Processor supports Intel(R) Streaming SIMD Extensions (Intel(R) SSE) instruction set */
ippCpuSSE2 = 0x41, /* Processor supports Intel(R) Streaming SIMD Extensions 2 (Intel(R) SSE2) instruction set */
ippCpuSSE3 = 0x42, /* Processor supports Intel(R) Streaming SIMD Extensions 3 (Intel(R) SSE3) instruction set */
ippCpuSSSE3 = 0x43, /* Processor supports Intel(R) Supplemental Streaming SIMD Extension 3 (Intel(R) SSSE3) instruction set */
ippCpuSSE41 = 0x44, /* Processor supports Intel(R) Streaming SIMD Extensions 4.1 (Intel(R) SSE4.1) instruction set */
ippCpuSSE42 = 0x45, /* Processor supports Intel(R) Streaming SIMD Extensions 4.2 (Intel(R) SSE4.2) instruction set */
ippCpuAVX = 0x46, /* Processor supports Intel(R) Advanced Vector Extensions (Intel(R) AVX) instruction set */
ippCpuAES = 0x47, /* Processor supports Intel(R) AES New Instructions */
ippCpuSHA = 0x48, /* Processor supports Intel(R) SHA New Instructions */
ippCpuF16RND = 0x49, /* Processor supports RDRRAND & Float16 instructions */
ippCpuAVX2 = 0x4a, /* Processor supports Intel(R) Advanced Vector Extensions 2 (Intel(R) AVX2) instruction set */
ippCpuADCOX = 0x4b, /* Processor supports ADCX and ADOX instructions */
ippCpuX8664 = 0x60 /* Processor supports 64 bit extension */
} IppCpuType;
#define ippCPUID_MMX 0x00000001 /* Intel Architecture MMX technology supported */
#define ippCPUID_SSE 0x00000002 /* Streaming SIMD Extensions */
#define ippCPUID_SSE2 0x00000004 /* Streaming SIMD Extensions 2 */
#define ippCPUID_SSE3 0x00000008 /* Streaming SIMD Extensions 3 */
#define ippCPUID_SSSE3 0x00000010 /* Supplemental Streaming SIMD Extensions 3 */
#define ippCPUID_MOVBE 0x00000020 /* The processor supports MOVBE instruction */
#define ippCPUID_SSE41 0x00000040 /* Streaming SIMD Extensions 4.1 */
#define ippCPUID_SSE42 0x00000080 /* Streaming SIMD Extensions 4.2 */
#define ippCPUID_AVX 0x00000100 /* Advanced Vector Extensions instruction set */
#define ippAVX_ENABLEDBYOS 0x00000200 /* The operating system supports AVX */
#define ippCPUID_AES 0x00000400 /* AES instruction */
#define ippCPUID_CLMUL 0x00000800 /* PCLMULQDQ instruction */
#define ippCPUID_ABR 0x00001000 /* Reserved */
#define ippCPUID_RDRAND 0x00002000 /* Read Random Number instructions */
#define ippCPUID_F16C 0x00004000 /* Float16 instructions */
#define ippCPUID_AVX2 0x00008000 /* Advanced Vector Extensions 2 instruction set */
#define ippCPUID_ADCOX 0x00010000 /* ADCX and ADOX instructions */
#define ippCPUID_RDSEED 0x00020000 /* The RDSEED instruction */
#define ippCPUID_PREFETCHW 0x00040000 /* The PREFETCHW instruction */
#define ippCPUID_SHA 0x00080000 /* Intel (R) SHA Extensions */
#define ippCPUID_KNC 0x80000000 /* Intel(R) Xeon Phi(TM) Coprocessor */
#define ippCPUID_GETINFO_A 0x616f666e69746567
typedef struct {
int major; /* e.g. 1 */
int minor; /* e.g. 2 */
int majorBuild; /* e.g. 3 */
int build; /* e.g. 10, always >= majorBuild */
char targetCpu[4]; /* corresponding to Intel(R) processor */
const char* Name; /* e.g. "ippsw7" */
const char* Version; /* e.g. "v1.2 Beta" */
const char* BuildDate; /* e.g. "Jul 20 99" */
} IppLibraryVersion;
typedef unsigned char Ipp8u;
typedef unsigned short Ipp16u;
typedef unsigned int Ipp32u;
typedef signed char Ipp8s;
typedef signed short Ipp16s;
typedef signed int Ipp32s;
typedef float Ipp32f;
typedef __INT64 Ipp64s;
typedef __UINT64 Ipp64u;
typedef double Ipp64f;
typedef struct {
Ipp64s re;
Ipp64s im;
} Ipp64sc;
typedef enum {
ippRndZero,
ippRndNear,
ippRndFinancial
} IppRoundMode;
typedef mfxSize IppiSize;
enum {
IPP_UPPER = 1,
IPP_LEFT = 2,
IPP_CENTER = 4,
IPP_RIGHT = 8,
IPP_LOWER = 16,
IPP_UPPER_LEFT = 32,
IPP_UPPER_RIGHT = 64,
IPP_LOWER_LEFT = 128,
IPP_LOWER_RIGHT = 256
};
/* /////////////////////////////////////////////////////////////////////////////
// The following enumerator defines a status of IPP operations
// negative value means error
*/
typedef enum {
/* errors */
ippStsNotSupportedModeErr = -9999,/* The requested mode is currently not supported. */
ippStsCpuNotSupportedErr = -9998,/* The target CPU is not supported. */
ippStsInplaceModeNotSupportedErr = -9997,/* The inplace operation is currently not supported. */
ippStsExceededSizeErr = -232, /* Requested size exceeded the maximum supported ROI size */
ippStsWarpDirectionErr = -231, /* The warp transform direction is illegal */
ippStsFilterTypeErr = -230, /* The filter type is incorrect or not supported */
ippStsNormErr = -229, /* The norm is incorrect or not supported */
ippStsAlgTypeErr = -228, /* Algorithm type is not supported. */
ippStsMisalignedOffsetErr = -227, /* The offset is not aligned with an element. */
ippStsQuadraticNonResidueErr = -226, /* SQRT operation on quadratic non-residue value. */
ippStsBorderErr = -225, /* Illegal value for border type.*/
ippStsDitherTypeErr = -224, /* Dithering type is not supported. */
ippStsH264BufferFullErr = -223, /* Buffer for the output bitstream is full. */
ippStsWrongAffinitySettingErr= -222, /* An affinity setting does not correspond to the affinity setting that was set by f.ippSetAffinity(). */
ippStsLoadDynErr = -221, /* Error when loading the dynamic library. */