Commit 0389645c authored by Carsten Schoenert's avatar Carsten Schoenert

Import Upstream version 23

parent eea7a2eb

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Ngspice-22
Copyright (c) 2010,
Ngspice-23
Copyright (c) 2011,
All rights reserved.
......@@ -13,7 +13,7 @@ to the work of researchers, electronic designers, software editors, etc.
The Ngspice team tries to collect work from the different sources and
contribute new functionalities. Thus, the material we manipulate is
heterogeneous in licenses. Keeping the licenses as is, is the way to live with
that diversity. For release 21 as well, we choose not to relicense.
that diversity. For release 23 as well, we choose not to relicense.
Copyleft is a fundamental question in FOSS development. The choice of a
copylefted contribution, or a non copylefted contribution is an important
......
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......@@ -47,13 +47,13 @@ Table of contents
11.5 MOS9 - Level 9 MOS model
11.6 BSIM1 - BSIM model level 1
11.7 BSIM2 - BSIM model level 2
11.8 BSIM3v0 - BSIM model level 3
11.9 BSIM3v1 - BSIM model level 3
11.10 BSIM3v1 - BSIM model level 3
11.11 BSIM3v1 - BSIM model level 3
11.12 BSIM3 - BSIM model level 3
11.13 BSIM4 - BSIM model level 4
11.14 HiSIM - Hiroshima-university STARC IGFET Model
11.8 BSIM3 - BSIM model level 3 vers. 0
11.9 BSIM3 - BSIM model level 3 vers. 1
11.10 BSIM3 - BSIM model level 3 vers. 2
11.11 BSIM3 - BSIM model level 3 vers. 3
11.12 BSIM4 - BSIM model level 4
11.13 HiSIM2 - Hiroshima-University STARC IGFET Model
11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
12. SOI devices
12.1 BSIM3SOI_FD - SOI model (fully depleted devices)
12.2 BSIM3SOI_DD - SOI Model (dynamic depletion model)
......@@ -368,12 +368,12 @@ will be updated every time the device specific code is altered or changed to ref
Ver: N/A
Class: Q
Level: 4
Level: 4 & 9
Dir: devices/vbic
Status:
This is the Vertical Bipolar InterCompany model. The author of VBIC is
Colin McAndrew mcandrew@ieee.org
This is the Vertical Bipolar InterCompany model in version 1.2. The author
of VBIC is Colin McAndrew mcandrew@ieee.org.
Spice3 Implementation: Dietmar Warning DAnalyse GmbH
Web Site: http://www.designers-guide.com/VBIC/index.html
......@@ -609,40 +609,21 @@ will be updated every time the device specific code is altered or changed to ref
Dir: devices/bsim3v0
Status: TO BE TESTED AND IMPROVED
11.9 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1
Dir: devices/bsim3v1
Status: TO BE TESTED
11.10 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1a
Dir: devices/bsim3v1a
Status: TO BE TESTED AND IMPROVED
This is the BSIM3v3.1 model modified by Alan Gillespie.
11.11 BSIM3v1 - BSIM model level 3
Ver: 3.1
Class: M
Level: 8 & 49, version = 3.1s
Dir: devices/bsim3v1s
Status: TO BE TESTED AND IMPROVED
This is the BSIM3v3.1 model modified by Serban Popescu.
This is level 49 model. It is an implementation that supports
"HDIF" and "M" parameters.
11.12 BSIM3 - BSIM model level 3
11.10 BSIM3 - BSIM model level 3
Ver: 3.2.4
Class: M
......@@ -658,12 +639,13 @@ will be updated every time the device specific code is altered or changed to ref
Enhancements over the original model:
- Parallel Multiplier
- delvto, mulu0 instance parameter
- ACM Area Calculation Method
- Multirevision code (supports all 3v3.2 minor revisions)
- NodesetFix
11.12 BSIM3 - BSIM model level 3
11.11 BSIM3 - BSIM model level 3
Ver: 3.3.0
Class: M
......@@ -685,7 +667,7 @@ will be updated every time the device specific code is altered or changed to ref
- Support for Multi-core processors using OpenMP
11.13 BSIM4 - BSIM model level 4
11.12 BSIM4 - BSIM model level 4
Ver: 4.2.0 - 4.6.5
Class: M
......@@ -704,23 +686,35 @@ will be updated every time the device specific code is altered or changed to ref
- Support for Multi-core processors using OpenMP
11.14 HiSIM - Hiroshima-university STARC IGFET Model
11.13 HiSIM2 - Hiroshima-university STARC IGFET Model
Ver: 1.2.0
Ver: 2.5.1
Class: M
Level: 64
Dir: devices/hisim
Level: 61
Dir: devices/hisim2
Status: TO BE TESTED.
This is the HiSIM model available from Hiroshima University
This is the HiSIM2 model available from Hiroshima University
(Ultra-Small Device Engineering Laboratory)
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
Enhancements over the original model:
- Parallel Multiplier
- NodesetFix
11.14 HiSIM_HV - Hiroshima-University STARC IGFET High Voltage Model
Ver: 1.2.1
Class: M
Level: 62
Dir: devices/hisimhv
Status: TO BE TESTED.
This is the HiSIM_HV model available from Hiroshima University
(Ultra-Small Device Engineering Laboratory)
Web site: http://home.hiroshima-u.ac.jp/usdl/HiSIM.html
12. SOI devices
......@@ -794,7 +788,7 @@ will be updated every time the device specific code is altered or changed to ref
Ver: 2.6
Class: M
Level: 62
Level: 61
Dir: devices/soi3
Status: OBSOLETE
......
Ngspice F.A.Q.Version 1.7 (rework-22 release)
Ngspice F.A.Q.Version 1.8 (rework-23 release)
Maintained by Paolo Nenzi, Holger Vogt
Last update: 25-09-2010
Last update: 05-06-2011
This document contains the Frequently Asked Questions (and Answers)
for ngspice project.
......@@ -236,26 +236,34 @@
The latest version released is:
* ngspice-rework-22 (released on 26/09/2010)
* ngspice-rework-23 (released on 05/06/2011)
2.2. What are the latest features in the current release?
New features:
+ OpenMP multicore support for BSIM3, BSIM4, and BSIMSOI4
+ reinstate {$var} expansion in interactive interpreter
+ .TITLE line added
+ update to 'spectrum' script
+ par('expression') in .four, .plot, .print, .meas, .save commands
+ command 'option' for use in spinit, .spiceinit, and in scripts
+ adms procedure updated
+ new random number generator, random functions sunif() and sgauss()
+ ngspice manual updated
Bug fixes:
+ Major code cleanup to reduce compiler/linker warnings: ansi function prototypes,
void/char pointers to named pointers, explicit type casts and many more
+ Many small bugs
- New features:
+ Reduction of trtol to 1 only if 'A' devices in the circuit and xspice is enabled
+ command wrs2p to write a s-parameter file using Touchstone vers. 1 format
+ d_source d_state d_ram, test cases for those xspice codemodels
+ transient noise simulation added to independent voltage and current sources
+ Random telegraph noise added to independent voltage and current sources
+ 'time = nnn' in stop command added
+ random voltage generator option trrandom to independent voltage and current sources
+ ngspice build possible in a separate directory (e.g. in ng-spice-rework/release)
+ update FIND .. WHEN measurements
+ diode & bjt temperature model update with tlev and tlevc
+ merge bsim3v1a code with bsim3v0 and bsim3v1s code with bsim3v1
+ bjt2: removed - all GP extensions of this model are now in the bjt model
+ HiSIM_HV model vers. 1.2.1 added
+ bsim3v32: delvto and mulu0 as instance parameters
+ Replace HiSIM1 by HiSIM_2.5.1_Release_20110407
- Bug fixes:
+ More on prototypes, type casts, reordering of functions, compiler warnings
+ allow models like 2N2904 or 2SK136 also in subcircuits
+ fix sensitvity calculation (for the dc-2+.cir testcase)
+ allow multiple call to setup w/ correct node collapsing
+ Many small bugs
......
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......@@ -37,8 +37,9 @@ subdir = .
DIST_COMMON = README $(am__configure_deps) $(srcdir)/Makefile.am \
$(srcdir)/Makefile.in $(srcdir)/config.h.in \
$(top_srcdir)/configure \
$(top_srcdir)/src/xspice/icm/GNUmakefile.in \
$(top_srcdir)/src/xspice/icm/makedefs.in AUTHORS COPYING \
ChangeLog INSTALL NEWS config.guess config.sub depcomp \
ChangeLog INSTALL NEWS compile config.guess config.sub depcomp \
install-sh ltmain.sh missing ylwrap
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/configure.ac
......@@ -48,7 +49,8 @@ am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
configure.lineno config.status.lineno
mkinstalldirs = $(install_sh) -d
CONFIG_HEADER = config.h
CONFIG_CLEAN_FILES = src/xspice/icm/makedefs
CONFIG_CLEAN_FILES = src/xspice/icm/makedefs \
src/xspice/icm/GNUmakefile
CONFIG_CLEAN_VPATH_FILES =
SOURCES =
DIST_SOURCES =
......@@ -115,9 +117,6 @@ AWK = @AWK@
CC = @CC@
CCDEPMODE = @CCDEPMODE@
CFLAGS = @CFLAGS@
CIDERDIR = @CIDERDIR@
CIDERSCRIPTS = @CIDERSCRIPTS@
CIDERSIM = @CIDERSIM@
CPP = @CPP@
CPPFLAGS = @CPPFLAGS@
CYGPATH_W = @CYGPATH_W@
......@@ -150,14 +149,10 @@ LTLIBOBJS = @LTLIBOBJS@
MAINT = @MAINT@
MAKEINFO = @MAKEINFO@
MKDIR_P = @MKDIR_P@
NDEV_DIR = @NDEV_DIR@
NDEV_LIB = @NDEV_LIB@
NM = @NM@
NMEDIT = @NMEDIT@
NOTVLADEVDIR = @NOTVLADEVDIR@
NOTXGRAPH = @NOTXGRAPH@
NUMDEV = @NUMDEV@
NUMDEVDIR = @NUMDEVDIR@
OBJDUMP = @OBJDUMP@
OBJEXT = @OBJEXT@
OTOOL = @OTOOL@
......@@ -179,15 +174,10 @@ TCL_PACKAGE_PATH = @TCL_PACKAGE_PATH@
VERSION = @VERSION@
VLADEV = @VLADEV@
VLADEVDIR = @VLADEVDIR@
WINDISPLIB = @WINDISPLIB@
WINMAIN = @WINMAIN@
XGRAPHDIR = @XGRAPHDIR@
XMKMF = @XMKMF@
XSPICEDIR = @XSPICEDIR@
XSPICEDLLIBS = @XSPICEDLLIBS@
XSPICEINIT = @XSPICEINIT@
XSPICELIB1 = @XSPICELIB1@
XSPICELIB2 = @XSPICELIB2@
XSPICETESTS = @XSPICETESTS@
X_CFLAGS = @X_CFLAGS@
X_EXTRA_LIBS = @X_EXTRA_LIBS@
X_LIBS = @X_LIBS@
......@@ -321,6 +311,8 @@ distclean-hdr:
-rm -f config.h stamp-h1
src/xspice/icm/makedefs: $(top_builddir)/config.status $(top_srcdir)/src/xspice/icm/makedefs.in
cd $(top_builddir) && $(SHELL) ./config.status $@
src/xspice/icm/GNUmakefile: $(top_builddir)/config.status $(top_srcdir)/src/xspice/icm/GNUmakefile.in
cd $(top_builddir) && $(SHELL) ./config.status $@
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