Commit ad4af16d authored by Ruben Undheim's avatar Ruben Undheim

Fix more lintians and properly clean up

parent 434680a9
Pipeline #41660 passed with stage
in 14 minutes and 30 seconds
......@@ -21,7 +21,7 @@ Depends: ${shlibs:Depends}, ${misc:Depends}
Description: Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a TCL interface for entering commands for analysing designs.
has a Tcl interface for entering commands for analysing designs.
.
It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
......@@ -33,7 +33,7 @@ Depends: ${misc:Depends}
Description: Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a TCL interface for entering commands for analysing designs.
has a Tcl interface for entering commands for analysing designs.
.
It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
......
......@@ -8,7 +8,7 @@ export DEB_LDFLAGS_MAINT_APPEND = -Wl,--as-needed
export DEB_BUILD_MAINT_OPTIONS = hardening=+all
%:
dh $@ --parallel
dh $@
override_dh_auto_install:
......@@ -16,3 +16,28 @@ override_dh_auto_install:
override_dh_auto_clean:
dh_auto_clean
$(RM) app/StaApp_wrap.cc
$(RM) app/TclInitVar.cc
$(RM) app/libOpenSTA.a
$(RM) app/sta
$(RM) liberty/LibertyExprLex.cc
$(RM) liberty/LibertyExprLex.hh
$(RM) liberty/LibertyExprParse.cc
$(RM) liberty/LibertyExprParse.hh
$(RM) liberty/LibertyLex.cc
$(RM) liberty/LibertyLex.hh
$(RM) liberty/LibertyParse.cc
$(RM) liberty/LibertyParse.hh
$(RM) parasitics/SpefLex.cc
$(RM) parasitics/SpefLex.hh
$(RM) parasitics/SpefParse.cc
$(RM) parasitics/SpefParse.hh
$(RM) sdf/SdfLex.cc
$(RM) sdf/SdfLex.hh
$(RM) sdf/SdfParse.cc
$(RM) sdf/SdfParse.hh
$(RM) util/StaConfig.hh
$(RM) verilog/VerilogLex.cc
$(RM) verilog/VerilogLex.hh
$(RM) verilog/VerilogParse.cc
$(RM) verilog/VerilogParse.hh
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