1. 06 May, 2013 1 commit
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  3. 13 Apr, 2012 1 commit
    • Tom Stellard's avatar
      radeonsi: initial WIP SI code · a75c6163
      Tom Stellard authored
      This commit adds initial support for acceleration
      on SI chips.  egltri is starting to work.
      
      The SI/R600 llvm backend is currently included in mesa
      but that may change in the future.
      
      The plan is to write a single gallium driver and
      use gallium to support X acceleration.
      
      This commit contains patches from:
      Tom Stellard <thomas.stellard@amd.com>
      Michel Dänzer <michel.daenzer@amd.com>
      Alex Deucher <alexander.deucher@amd.com>
      Vadim Girlin <vadimgirlin@gmail.com>
      Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
      
      The following commits were squashed in:
      
      ======================================================================
      
      radeonsi: Remove unused winsys pointer
      
      This was removed from r600g in commit:
      
      commit 96d88293
      Author: Marek Olšák <maraeo@gmail.com>
      Date:   Fri Feb 17 01:49:49 2012 +0100
      
          gallium: remove unused winsys pointers in pipe_screen and pipe_context
      
          A winsys is already a private object of a driver.
      
      ======================================================================
      
      radeonsi: Copy color clamping CAPs from r600
      
      Not sure if the values of these CAPS are correct for radeonsi, but the
      same changed were made to r600g in commit:
      
      commit bc1c8369
      Author: Marek Olšák <maraeo@gmail.com>
      Date:   Mon Jan 23 03:11:17 2012 +0100
      
          st/mesa: do vertex and fragment color clamping in shaders
      
          For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
          the perfect place for a fallback.
          The exceptions are:
          - r500 (vertex clamp only)
          - nv50 (both)
          - nvc0 (both)
          - softpipe (both)
      
          We also have to take into account that r300 can do CLAMPED vertex colors only,
          while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
          with the two new CAPs.
      
      ======================================================================
      
      radeonsi: Remove PIPE_CAP_OUTPUT_READ
      
      This CAP was dropped in commit:
      
      commit 04e32400
      Author: Marek Olšák <maraeo@gmail.com>
      Date:   Thu Feb 23 23:44:36 2012 +0100
      
          gallium: remove PIPE_SHADER_CAP_OUTPUT_READ
      
          r600g is the only driver which has made use of it. The reason the CAP was
          added was to fix some piglit tests when the GLSL pass lower_output_reads
          didn't exist.
      
          However, not removing output reads breaks the fallback for glClampColorARB,
          which assumes outputs are not readable. The fix would be non-trivial
          and my personal preference is to remove the CAP, considering that reading
          outputs is uncommon and that we can now use lower_output_reads to fix
          the issue that the CAP was supposed to workaround in the first place.
      
      ======================================================================
      
      radeonsi: Add missing parameters to rws->buffer_get_tiling() call
      
      This was changed in commit:
      
      commit c0c979ee
      Author: Jerome Glisse <jglisse@redhat.com>
      Date:   Mon Jan 30 17:22:13 2012 -0500
      
          r600g: add support for common surface allocator for tiling v13
      
          Tiled surface have all kind of alignment constraint that needs to
          be met. Instead of having all this code duplicated btw ddx and
          mesa use common code in libdrm_radeon this also ensure that both
          ddx and mesa compute those alignment in the same way.
      
          v2 fix evergreen
          v3 fix compressed texture and workaround cube texture issue by
             disabling 2D array mode for cubemap (need to check if r7xx and
             newer are also affected by the issue)
          v4 fix texture array
          v5 fix evergreen and newer, split surface values computation from
             mipmap tree generation so that we can get them directly from the
             ddx
          v6 final fix to evergreen tile split value
          v7 fix mipmap offset to avoid to use random value, use color view
             depth view to address different layer as hardware is doing some
             magic rotation depending on the layer
          v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
             evergreen, align bytes per pixel to a multiple of a dword
          v9 fix handling of stencil on evergreen, half fix for compressed
             texture
          v10 fix evergreen compressed texture proper support for stencil
              tile split. Fix stencil issue when array mode was clear by
              the kernel, always program stencil bo. On evergreen depth
              buffer bo need to be big enough to hold depth buffer + stencil
              buffer as even with stencil disabled things get written there.
          v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
              old ddx overestimate those. Fix linear case when pitch*height < 64.
              Fix r300g.
          v12 Fix linear case when pitch*height < 64 for old path, adapt to
              libdrm API change
          v13 add libdrm check
      Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
      
      ======================================================================
      
      radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY
      
      This was removed in commit:
      
      commit 62f44f67
      Author: Marek Olšák <maraeo@gmail.com>
      Date:   Mon Mar 5 13:45:00 2012 +0100
      
          Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"
      
          This reverts commit 09500863.
      
          It was decided to refactor the transfer API instead of adding workarounds
          to address the performance issues.
      
      ======================================================================
      
      radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.
      
      Reintroduced in commit 9d9afcb5.
      
      ======================================================================
      
      radeonsi: nuke the fallback for vertex and fragment color clamping
      
      Ported from r600g commit c2b800cf.
      
      ======================================================================
      
      radeonsi: don't expose transform_feedback2 without kernel support
      
      Ported from r600g commit 15146fd1.
      
      ======================================================================
      
      radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.
      
      Ported from r600g part of commit 171be755.
      
      ======================================================================
      
      radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.
      
      Ported from r600g commit f183cc9c.
      
      ======================================================================
      
      radeonsi: rework and consolidate stencilref state setting.
      
      Ported from r600g commit a2361946.
      
      ======================================================================
      
      radeonsi: cleanup setting DB_SHADER_CONTROL.
      
      Ported from r600g commit 3d061caa.
      
      ======================================================================
      
      radeonsi: Get rid of register masks.
      
      Ported from r600g commits
      3d061caa..9344ab38.
      
      ======================================================================
      
      radeonsi: get rid of r600_context_reg.
      
      Ported from r600g commits
      9344ab38..bed20f02.
      
      ======================================================================
      
      radeonsi: Fix regression from 'Get rid of register masks'.
      
      ======================================================================
      
      radeonsi: optimize r600_resource_va.
      
      Ported from r600g commit 669d8766.
      
      ======================================================================
      
      radeonsi: remove u8,u16,u32,u64 types.
      
      Ported from r600g commit 78293b99.
      
      ======================================================================
      
      radeonsi: merge r600_context with r600_pipe_context.
      
      Ported from r600g commit e4340c19.
      
      ======================================================================
      
      radeonsi: Miscellaneous context cleanups.
      
      Ported from r600g commits
      e4340c19..621e0db7.
      
      ======================================================================
      
      radeonsi: add a new simple API for state emission.
      
      Ported from r600g commits
      621e0db7..f6614056.
      
      ======================================================================
      
      radeonsi: Also remove sbu_flags member of struct r600_reg.
      
      Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
      so some code needs to be disabled for now.
      
      ======================================================================
      
      radeonsi: Miscellaneous simplifications.
      
      Ported from r600g commits 38bf2763 and
      b0337b67.
      
      ======================================================================
      
      radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.
      
      Ported from commit 8b4f7b06.
      
      ======================================================================
      
      radeonsi: Use a fake reloc to sleep for fences.
      
      Ported from r600g commit 8cd03b93.
      
      ======================================================================
      
      radeonsi: adapt to get_query_result interface change.
      
      Ported from r600g commit 4445e170.
      a75c6163
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