Commit 3190142d authored by Diana Chen's avatar Diana Chen Committed by gbsbuild

Add APIs for vSIA indirect call support:

AppendVISACFSymbolInst and AppendVISACFIndirectFuncCallInst

Change-Id: Ie954933aea49ddeb363337a4fb246cfbfdcc9fae
parent 6671cd34
......@@ -692,7 +692,7 @@ public:
unsigned return_size,
int line_no);
bool CISA_create_faddr_instruction(uint32_t funcID, VISA_opnd* dst, int line_no);
bool CISA_create_faddr_instruction(char* sym_name, VISA_opnd* dst, int line_no);
bool CISA_create_raw_send_instruction(ISA_Opcode opcode,
unsigned char modifier,
......
......@@ -602,8 +602,8 @@ void Stitch_Compiled_Units( common_isa_header header, std::list<G4_Kernel*>& com
ASSERT_USER( kernel != NULL, "Valid kernel not found when stitching compiled units");
if (hasIndirectCall)
{
// we have to include every function
{
// we have to include every function
for (auto&& cu : compilation_units)
{
if (!cu->fg.builder->getIsKernel())
......@@ -613,7 +613,7 @@ void Stitch_Compiled_Units( common_isa_header header, std::list<G4_Kernel*>& com
}
}
else
{
{
Enumerate_Callees(header, kernel, compilation_units, callee_index);
}
......@@ -696,11 +696,11 @@ void Stitch_Compiled_Units( common_isa_header header, std::list<G4_Kernel*>& com
}
// Append declarations and color attributes from all callees to kernel
for (auto it = callee_index.begin(); it != callee_index.end(); ++it )
for (auto it = callee_index.begin(); it != callee_index.end(); ++it )
{
G4_Kernel* callee = Get_Resolved_Compilation_Unit( header, compilation_units, (*it) );
for (auto curDcl : callee->Declares)
for (auto curDcl : callee->Declares)
{
kernel->Declares.push_back( curDcl );
}
......@@ -1978,7 +1978,7 @@ bool CISA_IR_Builder::CISA_create_sync_instruction(ISA_Opcode opcode)
return true;
}
bool CISA_IR_Builder::CISA_create_sbarrier_instruction(bool isSignal)
bool CISA_IR_Builder::CISA_create_sbarrier_instruction(bool isSignal)
{
int ret = m_kernel->AppendVISASplitBarrierInst(isSignal);
return ret == CM_SUCCESS;
......@@ -2340,7 +2340,7 @@ bool CISA_IR_Builder::CISA_create_rtwrite_3d_instruction(VISA_opnd* pred,
APPEND_NON_NULL_RAW_OPND( Z );
APPEND_NON_NULL_RAW_OPND( Stencil );
Common_ISA_Exec_Size executionSize = Get_Common_ISA_Exec_Size_From_Raw_Size(exec_size);
m_kernel->AppendVISA3dRTWriteCPS((VISA_PredOpnd*)pred, emask, executionSize, (VISA_VectorOpnd*)rti,
m_kernel->AppendVISA3dRTWriteCPS((VISA_PredOpnd*)pred, emask, executionSize, (VISA_VectorOpnd*)rti,
cntrls, surface, (VISA_RawOpnd*)r1Header, (VISA_VectorOpnd*)SamplerIndex, (VISA_VectorOpnd*)CPSCounter, numMsgSpecificOpnd, rawOpnds);
return true;
......@@ -2674,15 +2674,14 @@ bool CISA_IR_Builder::CISA_create_ifcall_instruction(VISA_opnd *pred_opnd,
int line_no) //last index
{
Common_ISA_Exec_Size executionSize = Get_Common_ISA_Exec_Size_From_Raw_Size(exec_size);
m_kernel->AppendVISACFIndirectFuncCallInst((VISA_PredOpnd *)pred_opnd, emask, executionSize,
m_kernel->AppendVISACFIndirectFuncCallInst((VISA_PredOpnd *)pred_opnd, emask, executionSize,
(VISA_VectorOpnd*) funcAddr, (uint8_t) arg_size, (uint8_t) return_size);
return true;
}
bool CISA_IR_Builder::CISA_create_faddr_instruction(uint32_t funcId,
VISA_opnd* dst, int line_no)
bool CISA_IR_Builder::CISA_create_faddr_instruction(char* sym_name, VISA_opnd* dst, int line_no)
{
m_kernel->AppendVISACFFuncAddrInst(funcId, (VISA_VectorOpnd*) dst);
m_kernel->AppendVISACFSymbolInst(std::string(sym_name), (VISA_VectorOpnd*) dst);
return true;
}
......
......@@ -32,6 +32,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <list>
#include <map>
#include <set>
#include <string>
#include "Gen4_IR.hpp"
#include "FlowGraph.h"
......@@ -525,7 +526,7 @@ public:
// number of predefined variables are included.
int num_general_dcl;
unsigned num_temp_dcl;
// number of temp GRF vars created to hold spilled addr/flag
// number of temp GRF vars created to hold spilled addr/flag
uint32_t numAddrFlagSpillLoc = 0;
std::vector<input_info_t*> m_inputVect;
......@@ -612,7 +613,7 @@ public:
bool isOpndAligned( G4_Operand *opnd, unsigned short &offset, int align_byte );
// check if opnd is or can be made "alignByte"-byte aligned. This function will change the underlying
// variable's alignment (e.g., make a scalar variable GRF-aligned) when possible to satisfy
// variable's alignment (e.g., make a scalar variable GRF-aligned) when possible to satisfy
// the alignment
bool isOpndAligned(G4_Operand* opnd, int alignByte)
{
......@@ -1053,7 +1054,7 @@ public:
//
// Create a declare that is hardwired to some phyiscal GRF.
// It is useful to implement various workarounds post RA where we want to directly
// It is useful to implement various workarounds post RA where we want to directly
// address some physical GRF.
// regOff is in unit of the declare type.
// caller is responsible for ensuring the resulting variable does not violate any HW restrictions
......@@ -1064,7 +1065,7 @@ public:
G4_Declare* dcl = createTempVar(numElements, type, Either, Any);
unsigned int linearizedStart = (regNum * G4_GRF_REG_NBYTES) + (regOff * getTypeSize(type));
// since it's called post RA (specifically post computePReg) we have to manually set the GRF's byte offset
dcl->setGRFBaseOffset(linearizedStart);
dcl->setGRFBaseOffset(linearizedStart);
dcl->getRegVar()->setPhyReg(phyregpool.getGreg(regNum), regOff);
return dcl;
}
......@@ -1339,19 +1340,19 @@ public:
case Type_D:
// It is legal to change a positive imm's type from signed to unsigned if it fits
// in the unsigned type. We do prefer signed type however for readability.
if (imm >= MIN_WORD_VALUE && imm <= MAX_WORD_VALUE)
if (imm >= MIN_WORD_VALUE && imm <= MAX_WORD_VALUE)
{
return Type_W;
}
else if (imm >= MIN_UWORD_VALUE && imm <= MAX_UWORD_VALUE)
}
else if (imm >= MIN_UWORD_VALUE && imm <= MAX_UWORD_VALUE)
{
return Type_UW;
}
else if (imm >= int(MIN_DWORD_VALUE) && imm <= int(MAX_DWORD_VALUE))
}
else if (imm >= int(MIN_DWORD_VALUE) && imm <= int(MAX_DWORD_VALUE))
{
return Type_D;
}
else if (imm >= unsigned(MIN_UDWORD_VALUE) && imm <= unsigned(MAX_UDWORD_VALUE))
}
else if (imm >= unsigned(MIN_UDWORD_VALUE) && imm <= unsigned(MAX_UDWORD_VALUE))
{
return Type_UD;
}
......@@ -1361,11 +1362,11 @@ public:
{
// unsigned imm must stay as unsigned
uint64_t immU = static_cast<uint64_t>(imm);
if (immU <= MAX_UWORD_VALUE)
if (immU <= MAX_UWORD_VALUE)
{
return Type_UW;
}
else if (immU <= unsigned(MAX_UDWORD_VALUE))
else if (immU <= unsigned(MAX_UDWORD_VALUE))
{
return Type_UD;
}
......@@ -1420,7 +1421,7 @@ public:
{
// Create new lab string with name of compilation unit
// to ensure unique label names across compilation units.
if (getOptions()->isTargetCM() && kind != LABEL_FC)
if (getOptions()->isTargetCM() && kind != LABEL_FC)
{
lab += std::string("_") + kernel.getName();
#if _DEBUG
......@@ -1905,7 +1906,8 @@ public:
uint8_t argSize,
uint8_t returnSize);
int translateVISACFFuncAddrInst(uint32_t funcId, G4_DstRegRegion* dst);
int translateVISACFSymbolInst(const std::string& symbolName,
G4_DstRegRegion* dst);
int translateVISACFFretInst(Common_ISA_Exec_Size execsize,
Common_VISA_EMask_Ctrl emask,
......@@ -2313,7 +2315,7 @@ public:
VISASampler3DSubOpCode actualop,
bool pixelNullMask,
bool cpsEnable,
bool uniformSampler,
bool uniformSampler,
G4_Predicate* pred,
Common_ISA_Exec_Size executionSize,
Common_VISA_EMask_Ctrl emask,
......
......@@ -780,8 +780,8 @@ static void readInstructionCommonNG(unsigned& bytePos, const char* buf, ISA_Opco
kernelBuilder->CreateVISAImmediate(mask, &value, ISA_TYPE_UW);
}
kernelBuilder->AppendVISAWaitInst(mask);
}
else if (opcode == ISA_SBARRIER)
}
else if (opcode == ISA_SBARRIER)
{
uint32_t mode = readOtherOperandNG(bytePos, buf, ISA_TYPE_UB);
kernelBuilder->AppendVISASplitBarrierInst(mode != 0);
......@@ -1238,9 +1238,9 @@ static void readInstructionControlFlow(unsigned& bytePos, const char* buf, ISA_O
}
case ISA_FADDR:
{
uint16_t funcId = readPrimitiveOperandNG<uint16_t>(bytePos, buf);
uint16_t sym_name_idx = readPrimitiveOperandNG<uint16_t>(bytePos, buf);
VISA_VectorOpnd* dst = readVectorOperandNG(bytePos, buf, container, true);
kernelBuilder->AppendVISACFFuncAddrInst(funcId, dst);
kernelBuilder->AppendVISACFSymbolInst(container.stringPool[sym_name_idx], dst);
return;
}
case ISA_SWITCHJMP:
......@@ -1727,7 +1727,7 @@ static void readInstructionSampler(unsigned& bytePos, const char* buf, ISA_Opcod
{
// 0x6D <op> <pixel_null_mask> <cps_enable> <exec_size> <pred>
// <channels> <aoffimmi> <sampler> <surface> <dst> <numParams> <params>
auto op = readSubOpcodeByteNG(bytePos, buf);
auto op = readSubOpcodeByteNG(bytePos, buf);
Common_VISA_EMask_Ctrl emask = vISA_EMASK_M1;
Common_ISA_Exec_Size esize = EXEC_SIZE_ILLEGAL;
......
......@@ -427,6 +427,7 @@ VISA_RawOpnd* rawOperandArray[16];
//%type <string> KERNEL_NAME
%type <string> PredCntrl
%type <string> FUNCTION_NAME
%type <string> SymbolName
%type <number> PlaneID
%type <number> SIMDMode
......@@ -838,7 +839,7 @@ GEN_ATTR : /* Empty */
$$.value = (int)$4;
$$.attr_set = true;
};
| DIRECTIVE_ATTR VAR '='
| DIRECTIVE_ATTR VAR '='
{
$$.name = $2;
$$.isInt = false;
......@@ -1072,13 +1073,13 @@ ScatterTypedInstruction : Predicate SCATTER_TYPED_OP SAMPLER_CHANNEL ExecSi
pCisaBuilder->CISA_create_scatter4_typed_instruction($2, $1.cisa_gen_opnd, ChannelMask::createFromAPI($3), $4.emask, $4.exec_size, $5, $6.cisa_gen_opnd, $7.cisa_gen_opnd, $8.cisa_gen_opnd, $9.cisa_gen_opnd, $10.cisa_gen_opnd, CISAlineno);
};
// 1 2 3 4 5 6 7 8
// 1 2 3 4 5 6 7 8
Scatter4ScaledInstruction : Predicate SCATTER4_SCALED_OP SAMPLER_CHANNEL ExecSize VAR VecSrcOperand_G_I_IMM RawOperand RawOperand
{
pCisaBuilder->CISA_create_scatter4_scaled_instruction($2, $1.cisa_gen_opnd, $4.emask, $4.exec_size, ChannelMask::createFromAPI($3), $5, $6.cisa_gen_opnd, $7.cisa_gen_opnd, $8.cisa_gen_opnd, CISAlineno);
};
// 1 2 3 4 5 6 7 8 9
// 1 2 3 4 5 6 7 8 9
ScatterScaledInstruction : Predicate SCATTER_SCALED_OP '.' NUMBER ExecSize VAR VecSrcOperand_G_I_IMM RawOperand RawOperand
{
pCisaBuilder->CISA_create_scatter_scaled_instruction($2, $1.cisa_gen_opnd, $5.emask, $5.exec_size, (uint32_t) $4, $6, $7.cisa_gen_opnd, $8.cisa_gen_opnd, $9.cisa_gen_opnd, CISAlineno);
......@@ -1175,7 +1176,7 @@ RTWriteOperandParse: /* empty */
{
RTWriteOperands.push_back($2.cisa_gen_opnd);
}
// 1 2 3 4 5 6
// 1 2 3 4 5 6
RTWriteInstruction: Predicate RTWRITE_OP_3D RTWRITE_MODE ExecSize VAR RTWriteOperandParse
{
pCisaBuilder->CISA_create_rtwrite_3d_instruction( $1.cisa_gen_opnd, $3, $4.emask, (unsigned int)$4.exec_size, $5,
......@@ -1259,12 +1260,12 @@ SVM_OP ExecSize VecSrcOperand_G_I_IMM RawOperand
{
pCisaBuilder->CISA_create_svm_atomic_instruction($1.cisa_gen_opnd, $5.emask, $5.exec_size, $3, $4, $6.cisa_gen_opnd, $8.cisa_gen_opnd, $9.cisa_gen_opnd, $7.cisa_gen_opnd, CISAlineno);
}
// 1 2 3 4 5 6 7
// 1 2 3 4 5 6 7
| Predicate SVM_GATHER4SCALED_OP SAMPLER_CHANNEL ExecSize VecSrcOperand_G_I_IMM RawOperand RawOperand
{
pCisaBuilder->CISA_create_svm_gather4_scaled($1.cisa_gen_opnd, $4.emask, $4.exec_size, ChannelMask::createFromAPI($3), $5.cisa_gen_opnd, $6.cisa_gen_opnd, $7.cisa_gen_opnd, CISAlineno);
}
// 1 2 3 4 5 6 7
// 1 2 3 4 5 6 7
| Predicate SVM_SCATTER4SCALED_OP SAMPLER_CHANNEL ExecSize VecSrcOperand_G_I_IMM RawOperand RawOperand
{
pCisaBuilder->CISA_create_svm_scatter4_scaled($1.cisa_gen_opnd, $4.emask, $4.exec_size, ChannelMask::createFromAPI($3), $5.cisa_gen_opnd, $6.cisa_gen_opnd, $7.cisa_gen_opnd, CISAlineno);
......@@ -1311,13 +1312,13 @@ BranchInstruction : Predicate BRANCH_OP ExecSize TargetLabel
// 1 2 3 4 5 6
| Predicate IFCALL ExecSize VecSrcOperand_G_I_IMM NUMBER NUMBER
{
pCisaBuilder->CISA_create_ifcall_instruction($1.cisa_gen_opnd, $3.emask, $3.exec_size,
pCisaBuilder->CISA_create_ifcall_instruction($1.cisa_gen_opnd, $3.emask, $3.exec_size,
$4.cisa_gen_opnd, (unsigned)$5, (unsigned)$6, CISAlineno);
}
// 1 2 3
| FADDR NUMBER VecDstOperand_G_I
// 1 2 3
| FADDR SymbolName VecDstOperand_G_I
{
pCisaBuilder->CISA_create_faddr_instruction((uint32_t) $2, $3.cisa_gen_opnd, CISAlineno);
pCisaBuilder->CISA_create_faddr_instruction($2, $3.cisa_gen_opnd, CISAlineno);
}
// 1 2 3
......@@ -1417,6 +1418,9 @@ TargetLabel: VAR
| F_NAME
{ $$ = $1; };
SymbolName: VAR
{ $$ = $1; };
/* ------ predicate and Modifiers ------ */
......@@ -1561,7 +1565,7 @@ VecSrcOpndSimple : VAR TwoDimOffset
$$.type = OPERAND_GENERAL;
$$.cisa_gen_opnd = pCisaBuilder->CISA_create_gen_src_operand($1, 1, 1, 0, $2.row, $2.elem, MODIFIER_NONE, CISAlineno);
};
// 1 2 3 4 5
VMEOpndIME : '(' NUMBER ',' NUMBER ')'
{
......
......@@ -487,14 +487,14 @@ void FlowGraph::preprocess(INST_LIST& instlist)
{
G4_INST* i = *I;
if (i->opcode() == G4_goto)
{
{
G4_Label* target = i->asCFInst()->getUip()->asLabel();
assert(labels.count(target) && "undefined goto label");
assert(labels.count(target) && "undefined goto label");
}
else if ((i->opcode() == G4_jmpi || i->isCall()) && i->getSrc(0) && i->getSrc(0)->isLabel())
{
assert(labels.count((G4_Label *)i->getSrc(0)) && "undefined jmpi/call label");
}
}
}
#endif
......@@ -643,7 +643,7 @@ void FlowGraph::constructFlowGraph(INST_LIST& instlist)
{
G4_BB* next_BB = beginBB(labelMap, next_i);
// next_BB may be null if the kernel ends on an CF inst (e.g., backwward goto/jmpi)
// This should be ok because we should not fall-through to next_BB in such case
// This should be ok because we should not fall-through to next_BB in such case
// (i.e., goto/jmpi must not be predicated)
{
if (i->opcode() == G4_jmpi || i->isCall())
......@@ -4096,7 +4096,7 @@ void G4_BB::emitInstructionInfo(std::ostream& output, INST_LIST_ITER &it)
char* curFilename = (*it)->getSrcFilename();
int curSrcLineNo = (*it)->getLineNo();
if ((*it)->isLabel())
if ((*it)->isLabel())
{
return;
}
......@@ -4106,7 +4106,7 @@ void G4_BB::emitInstructionInfo(std::ostream& output, INST_LIST_ITER &it)
emitFile = true;
}
if (prevSrcLineNo != curSrcLineNo && curSrcLineNo != 0)
if (prevSrcLineNo != curSrcLineNo && curSrcLineNo != 0)
{
emitLineNo = true;
}
......@@ -5490,7 +5490,7 @@ void writeBuffer(std::vector<unsigned char>& buffer, unsigned int& bufferSize, c
void* gtPinData::getGTPinInfoBuffer(unsigned int &bufferSize)
{
gtpin::igc::igc_init_t t;
std::vector<unsigned char> buffer;
std::vector<unsigned char> buffer;
unsigned int numTokens = 0;
bufferSize = 0;
......@@ -5628,54 +5628,8 @@ unsigned int G4_Kernel::getNumCalleeSaveRegs()
void RelocationEntry::doRelocation(const G4_Kernel& kernel, void* binary, uint32_t binarySize)
{
uint32_t instOffset = (uint32_t)inst->getGenOffset();
assert(instOffset < binarySize && "invalid offset for relocation instruction");
switch (relocType)
{
case RelocationType::IndirectCall:
{
uint32_t relocVal = (uint32_t)indirectCallInst->getGenOffset();
assert(relocVal < binarySize && "invalid relocation offset");
iga::ImmVal iga_imm;
iga_imm.kind = iga::ImmVal::U32;
iga_imm.u32 = relocVal;
bool status = KernelEncoder::patchImmValue(
*iga::Model::LookupModel(BinaryEncodingIGA::getIGAInternalPlatform(getGenxPlatform())),
(unsigned char*)binary + instOffset,
BinaryEncodingIGA::getIGAType(Type_UD),
iga_imm);
assert(status == true);
break;
}
case RelocationType::FunctionAddr:
{
G4_Kernel* callee = kernel.getCallee(funcId);
assert(callee && "callee not found");
if (callee)
{
auto firstInst = callee->getFirstNonLabelInst();
if (firstInst)
{
uint32_t relocVal = (uint32_t) firstInst->getGenOffset();
assert(relocVal < binarySize && "invalid relocation offset");
iga::ImmVal iga_imm;
iga_imm.kind = iga::ImmVal::U32;
iga_imm.u32 = relocVal;
bool status = KernelEncoder::patchImmValue(
*iga::Model::LookupModel(BinaryEncodingIGA::getIGAInternalPlatform(getGenxPlatform())),
(unsigned char*)binary + instOffset,
BinaryEncodingIGA::getIGAType(Type_UD),
iga_imm);
assert(status == true);
}
}
break;
}
default:
assert(false && "unhandled relocation type");
}
// FIXME: nothing to do here
// we have only dynamic relocations now, which cannot be resolved at compilation time
}
void RelocationEntry::dump() const
......@@ -5685,11 +5639,8 @@ void RelocationEntry::dump() const
inst->dump();
switch (relocType)
{
case RelocationType::IndirectCall:
std::cerr << "call inst (offset=" << indirectCallInst->getGenOffset() << "):\t";
indirectCallInst->dump();
case RelocationType::FunctionAddr:
std::cerr << "function id = " << funcId;
case RelocationType::R_SYM_ADDR:
std::cerr << "R_SYM_ADDR: symbol name = " << symName;
}
std::cerr << "\n";
}
......
......@@ -33,6 +33,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <unordered_set>
#include <unordered_map>
#include <set>
#include <string>
#include <unordered_set>
#include "cm_portability.h"
......@@ -351,7 +352,7 @@ public:
{
instList.splice(pos, otherBB->getInstList(), it);
}
void splice(INST_LIST::const_iterator pos, INST_LIST& other,
void splice(INST_LIST::const_iterator pos, INST_LIST& other,
INST_LIST::const_iterator first, INST_LIST::const_iterator last)
{
instList.splice(pos, other, first, last);
......@@ -375,7 +376,7 @@ public:
traversal(0), idom(NULL), beforeCall(NULL),
afterCall(NULL), calleeInfo(NULL), BBType(G4_BB_NONE_TYPE),
inNaturalLoop(false), loopNestLevel(0), scopeID(0), inSimdFlow(false),
start_block(NULL), physicalPred(NULL), physicalSucc(NULL), parent(fg),
start_block(NULL), physicalPred(NULL), physicalSucc(NULL), parent(fg),
instList(alloc), hasSendInBB(false)
{
}
......@@ -692,7 +693,7 @@ public:
// If you need to change the block ordering for any reason, create another data structure instead of
// modifying this one
BB_LIST BBs;
std::list<Edge> backEdges; // list of all backedges (tail->head)
Loop naturalLoops;
......@@ -780,9 +781,9 @@ public:
G4_Declare*& getStackPtrDcl() {return stackPtrDcl;}
G4_Declare*& getScratchRegDcl() {return scratchRegDcl;}
bool isPseudoVCADcl(G4_Declare* dcl) const
{
return std::find(pseudoVCADclList.begin(), pseudoVCADclList.end(), dcl) != std::end(pseudoVCADclList);
bool isPseudoVCADcl(G4_Declare* dcl) const
{
return std::find(pseudoVCADclList.begin(), pseudoVCADclList.end(), dcl) != std::end(pseudoVCADclList);
}
bool isPseudoVCEDcl(G4_Declare* dcl) const { return dcl == pseudoVCEDcl; }
bool isPseudoA0Dcl(G4_Declare* dcl) const
......@@ -972,7 +973,7 @@ public:
G4_BB* curBB = *bb_it;
G4_INST* last_inst = NULL;
if (!curBB->empty())
if (!curBB->empty())
{
last_inst = curBB->back();
......@@ -1150,9 +1151,9 @@ public:
// of free GRFs. It is meant to be freed by caller after
// last use of the buffer.
void* getFreeGRFInfo(unsigned int& size);
void setGTPinInit(void* buffer);
gtpin::igc::igc_init_t* getGTPinInit() { return gtpin_init; }
// return igc_info_t format buffer. caller casts it to igc_info_t.
......@@ -1182,34 +1183,23 @@ private:
enum class RelocationType
{
IndirectCall, // patched value is the address of an indirect call inst
FunctionAddr, // patched value is the address of a function
R_SYM_ADDR // patched value is the address of a symbol
};
class RelocationEntry
{
G4_INST* inst; // instruction to be relocated
int opndPos; // operand to be relocated. This should be a RelocImm
G4_INST* inst; // instruction to be relocated
int opndPos; // operand to be relocated. This should be a RelocImm
RelocationType relocType;
G4_INST* indirectCallInst = nullptr; // the call inst for the indirect call relocation
uint32_t funcId = (uint32_t) -1; // the function id for function address relocation
std::string symName; // the symbol name that it's address to be resolved
RelocationEntry(G4_INST* i, int pos, RelocationType type, G4_INST* call) :
inst(i), opndPos(pos), relocType(type), indirectCallInst(call) {}
RelocationEntry(G4_INST* i, int pos, RelocationType type, uint32_t functionId) :
inst(i), opndPos(pos), relocType(type), funcId(functionId) {}
RelocationEntry(G4_INST* i, int pos, RelocationType type, const std::string& symbolName) :
inst(i), opndPos(pos), relocType(type), symName(symbolName) {}
public:
static RelocationEntry createIndirectCallReloc(G4_INST* inst, int opndPos, G4_INST* callInst)
{
RelocationEntry entry(inst, opndPos, RelocationType::IndirectCall, callInst);
return entry;
}
static RelocationEntry createFuncAddrReloc(G4_INST* inst, int opndPos, uint32_t funcId)
static RelocationEntry createSymbolAddrReloc(G4_INST* inst, int opndPos, const std::string& symbolName)
{
RelocationEntry entry(inst, opndPos, RelocationType::FunctionAddr, funcId);
RelocationEntry entry(inst, opndPos, RelocationType::R_SYM_ADDR, symbolName);
return entry;
}
......@@ -1227,12 +1217,10 @@ public:
{
switch (relocType)
{
case RelocationType::IndirectCall:
return "IndirectCall";
case RelocationType::FunctionAddr:
return "FunctionAddress";
case RelocationType::R_SYM_ADDR:
return "R_SYM_ADDR";
default:
assert(false && "unhanlded relocation type");
assert(false && "unhandled relocation type");
return "";
}
}
......@@ -1242,16 +1230,10 @@ public:
return opndPos;
}
G4_INST* getIndirectCallInst() const
const std::string& getSymbolName() const
{
assert(relocType == RelocationType::IndirectCall && "invalid relocation type");
return indirectCallInst;
}
uint32_t getFunctionId() const
{
assert(relocType == RelocationType::FunctionAddr && "invalid relocation type");
return funcId;
assert(relocType == RelocationType::R_SYM_ADDR && "invalid relocation type");
return symName;
}
void doRelocation(const G4_Kernel& k, void* binary, uint32_t binarySize);
......@@ -1300,9 +1282,9 @@ class G4_Kernel
std::vector<RelocationEntry> relocationTable;
// id -> function map for all functions (transitively) called by this kernel
// this differs from the "callees" in IR_Builder as the one in builder only contain
// this differs from the "callees" in IR_Builder as the one in builder only contain
// functions directly called by this kernel
// this is populated for kernel only
// this is populated for kernel only
std::unordered_map<uint32_t, G4_Kernel*> allCallees;
public:
......@@ -1314,8 +1296,8 @@ public:
G4_Kernel(INST_LIST_NODE_ALLOCATOR& alloc,
Mem_Manager &m, Options *options, unsigned char major, unsigned char minor)
: m_options(options), RAType(RA_Type::UNKNOWN_RA), fg(alloc, this, m),
major_version(major), minor_version(minor), asmInstCount(0), kernelID(0),
: m_options(options), RAType(RA_Type::UNKNOWN_RA), fg(alloc, this, m),
major_version(major), minor_version(minor), asmInstCount(0), kernelID(0),
tokenInstructionCount(0), tokenReuseCount(0), AWTokenReuseCount(0),
ARTokenReuseCount(0), AATokenReuseCount(0), mathInstCount(0), syncInstCount(0),mathReuseCount(0),
ARSyncInstCount(0), AWSyncInstCount(0),
......@@ -1361,7 +1343,7 @@ public:
void setTokenReuseCount(int count) {tokenReuseCount= count; }
uint32_t getTokenReuseCount() {return tokenReuseCount; }
void setAWTokenReuseCount(int count) {AWTokenReuseCount= count; }
uint32_t getAWTokenReuseCount() {return AWTokenReuseCount; }
......@@ -1394,7 +1376,7 @@ public:
void setBankBadNum(int num) {bank_bad_num = num; }
uint32_t getBankBadNum() {return bank_bad_num; }
void setKernelID(uint64_t ID) { kernelID = ID; }
uint64_t getKernelID() const { return kernelID; }
......@@ -1413,7 +1395,7 @@ public:
unsigned getNumRegTotal() {return numRegTotal;}
void emit_asm(std::ostream& output, bool beforeRegAlloc, void * binary, uint32_t binarySize);
void emit_dep(std::ostream& output);
void evalAddrExp(void);
void dumpDotFile(const char* appendix);
......@@ -1444,7 +1426,7 @@ public:
}
gtPinData* getGTPinData()
{
{
if(!gtPinInfo)
allocGTPinData();
......@@ -1506,7 +1488,7 @@ class SCCAnalysis
// implements Tarjan's SCC algorithm
//
const FlowGraph& cfg;
// node used during the SCC algorithm
struct SCCNode
{
......@@ -1531,7 +1513,7 @@ class SCCAnalysis
G4_BB* root;
// list of BBs belonging to the SCC (including root as last BB)
// assumption is SCC is small (10s of BBs) so membership test is cheap
std::vector<G4_BB*> body;
std::vector<G4_BB*> body;
public:
SCC(G4_BB* bb) : root(bb) {} // root gets pushed to body just like other BBs in SCC
......@@ -1545,9 +1527,9 @@ class SCCAnalysis
}
// get earliest BB in program order (this is not necessarily the root depending on DFS order)
// assumption is reassingBBId() is called
G4_BB* getEarliestBB() const
G4_BB* getEarliestBB() const
{
auto result = std::min_element(body.begin(), body.end(),
auto result = std::min_element(body.begin(), body.end(),
[](G4_BB* bb1, G4_BB* bb2) {return bb1->getId() < bb2->getId(); });
return *result;
}
......
This diff is collapsed.
This diff is collapsed.
......@@ -630,7 +630,7 @@ static void printAtomicSubOpc(stringstream &sstr, uint8_t value)
{
sstr << ".16";
}
else if ((value >> 6) == 1)
else if ((value >> 6) == 1)
{
sstr << ".64";
}
......@@ -844,7 +844,7 @@ static string printInstructionCommon(const common_isa_header& isaHeader, const k
{
sstr << printOperand(isaHeader, header, inst, 0, opt);
}
else if (opcode == ISA_SBARRIER)
else if (opcode == ISA_SBARRIER)
{
uint8_t mode = getPrimitiveOperand<uint8_t>(inst, i);
sstr << (mode ? ".signal" : ".wait");
......@@ -940,7 +940,9 @@ static string printInstructionControlFlow(const common_isa_header& isaHeader, co
}
case ISA_FADDR:
{
sstr << getPrimitiveOperand<uint16_t>(inst, i++);
/// symbol name in string
sstr << header->strings[getPrimitiveOperand<uint16_t>(inst, i++)];
/// dst
sstr << printOperand(isaHeader, header, inst, i++, opt);
break;
}
......@@ -1361,7 +1363,7 @@ static string printInstructionSampler(const common_isa_header& isaHeader, const
sstr << SAMPLE_OP_3D_NAME[subop.opcode] << ".";
// Print the pixel null mask if it is enabled.
if (subop.pixelNullMask)
if (subop.pixelNullMask)
{
sstr << "pixel_null_mask.";
}
......@@ -1412,7 +1414,7 @@ static string printInstructionSampler(const common_isa_header& isaHeader, const
sstr << SAMPLE_OP_3D_NAME[subop.opcode] << ".";
// Print the pixel null mask if it is enabled.
// The last '.' is for the channels.
if (subop.pixelNullMask)
if (subop.pixelNullMask)
{
sstr << "pixel_null_mask.";
}
......@@ -1450,7 +1452,7 @@ static string printInstructionSampler(const common_isa_header& isaHeader, const
sstr << SAMPLE_OP_3D_NAME[subop.opcode] << ".";
// Print the pixel null mask if it is enabled.
// The last '.' is for the channels.
if (subop.pixelNullMask)
if (subop.pixelNullMask)
{
sstr << "pixel_null_mask.";
}
......
This diff is collapsed.
......@@ -376,7 +376,7 @@ public:
Common_VISA_EMask_Ctrl emask, Common_ISA_Exec_Size executionSize,
VISA_VectorOpnd* funcAddr, uint8_t argSize, uint8_t returnSize);
CM_BUILDER_API int AppendVISACFFuncAddrInst(uint32_t funcID, VISA_VectorOpnd* dst);
CM_BUILDER_API int AppendVISACFSymbolInst(std::string symbolName, VISA_VectorOpnd* dst);
CM_BUILDER_API int AppendVISACFFunctionRetInst(VISA_PredOpnd *pred, Common_VISA_EMask_Ctrl emask, Common_ISA_Exec_Size executionSize);
......
This diff is collapsed.
......@@ -344,11 +344,11 @@ public:
Common_VISA_EMask_Ctrl emask, Common_ISA_Exec_Size executionSize, VISA_VectorOpnd* funcAddr,
unsigned char argSize, unsigned char returnSize) = 0;
/// AppendVISACFFuncAddrInst -- stores the address of function <funcId> into <dst>
/// faddr funcId dst
/// funcId is the id of the function whose address is taken