Commit 414c4585 authored by wchen37's avatar wchen37 Committed by Paige, Alexander

make gen11-related vISA code open source

Change-Id: Ic4d3fb0e5ddae9500c098c6403de548ba0c9221d
parent 8294adef
......@@ -152,6 +152,24 @@ static inline int GetOperandSrcHDLImmType(G4_Type srcType)
default: MUST_BE_TRUE(false, "invalid type"); break;
}
}
else
{
switch (srcType) {
case Type_UD: type = G11HDL::SRCIMMTYPE_UD; break;
case Type_D: type = G11HDL::SRCIMMTYPE_D; break;
case Type_UW: type = G11HDL::SRCIMMTYPE_UW; break;
case Type_W: type = G11HDL::SRCIMMTYPE_W; break;
case Type_UV: type = G11HDL::SRCIMMTYPE_UV; break;
case Type_VF: type = G11HDL::SRCIMMTYPE_VF; break;
case Type_V: type = G11HDL::SRCIMMTYPE_V; break;
case Type_F: type = G11HDL::SRCIMMTYPE_F; break;
case Type_UQ: type = G11HDL::SRCIMMTYPE_UQ; break;
case Type_Q: type = G11HDL::SRCIMMTYPE_Q; break;
case Type_DF: type = G11HDL::SRCIMMTYPE_DF; break;
case Type_HF: type = G11HDL::SRCIMMTYPE_HF; break;
default: MUST_BE_TRUE(false, "invalid type"); break;
}
}
return type;
}
......@@ -179,6 +197,24 @@ static inline int GetOperandSrcHDLType(G4_Type regType)
default: MUST_BE_TRUE(false, "invalid type"); break;
}
}
else
{
switch(regType)
{
case Type_UD: type = G11HDL::SRCTYPE_UD; break;
case Type_D: type = G11HDL::SRCTYPE_D; break;
case Type_UW: type = G11HDL::SRCTYPE_UW; break;
case Type_W: type = G11HDL::SRCTYPE_W; break;
case Type_UB: type = G11HDL::SRCTYPE_UB; break;
case Type_B: type = G11HDL::SRCTYPE_B; break;
case Type_DF: type = G11HDL::SRCTYPE_DF; break;
case Type_F: type = G11HDL::SRCTYPE_F; break;
case Type_UQ: type = G11HDL::SRCTYPE_UQ; break;
case Type_Q: type = G11HDL::SRCTYPE_Q; break;
case Type_HF: type = G11HDL::SRCTYPE_HF; break;
default: MUST_BE_TRUE(false, "invalid type"); break;
}
}
return type;
}
......@@ -201,6 +237,14 @@ void BinaryEncodingCNL::EncodeOpCode(G4_INST* inst,
G9HDL::EU_OPCODE BinaryEncodingCNL::getEUOpcode(G4_opcode g4opc)
{
switch (g4opc)
{
// GEN11 specific
case G4_ror: return G9HDL::EU_OPCODE_ROR;
case G4_rol: return G9HDL::EU_OPCODE_ROL;
case G4_dp4a: return G9HDL::EU_OPCODE_DP4A;
default: break;
}
return (G9HDL::EU_OPCODE)BinaryEncodingBase::getEUOpcode(g4opc);
}
......@@ -2078,7 +2122,7 @@ BinaryEncodingCNL::Status BinaryEncodingCNL::DoAllEncodingJMPI(G4_INST* inst)
//hardcode:
brOneSrc.GetOperandControl().SetDestinationRegisterFile(G9HDL::REGFILE_ARF);
brOneSrc.GetOperandControl().SetDestinationDataType(G9HDL::DSTTYPE_UD);
brOneSrc.GetOperandControl().SetDestinationDataType(getGenxPlatform() == GENX_CNL ? G9HDL::DSTTYPE_UD : G11HDL::DSTTYPE_UD);
brOneSrc.GetOperandControl().SetDestinationAddressingMode(G9HDL::ADDRMODE_DIRECT);
//FIXME: bxml does not have arch reg file enumerations
......@@ -2417,7 +2461,8 @@ void BinaryEncodingCNL::DoAll()
BDWCompactSubRegTable.AddIndex1(IVBCompactSubRegTable[i] & 0x1F, i);
BDWCompactSubRegTable.AddIndex2(IVBCompactSubRegTable[i] & 0x3FF, i);
if (getGenxPlatform() > GENX_CNL)
{
{
BDWCompactDataTypeTableStr.AddIndex(ICLCompactDataTypeTable[i], i);
}
else
{
......
......@@ -80,6 +80,8 @@ typedef uint64_t QWORD;
#pragma pack(push, 1)
#include "IGfxHwEuIsaCNL.h"
#include "IGfxHwEuIsaICL.h"
/// \brief Class encapsulating encoding machinery using new auto-generated headers
///
......@@ -352,6 +354,45 @@ public:
}
else
{
switch (regType)
{ //BXML bug Line 851: bitrange 5-8, should be: 37-40
case Type_UD:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UD);
break;
case Type_D:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_D);
break;
case Type_UW:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UW);
break;
case Type_W:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_W);
break;
case Type_UB:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UB);
break;
case Type_B:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_B);
break;
case Type_DF:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_DF);
break;
case Type_F:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_F);
break;
case Type_UQ:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UQ);
break;
case Type_Q:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_Q);
break;
case Type_HF:
opnds.SetDestinationDataType(G11HDL::DSTTYPE_HF);
break;
default:
MUST_BE_TRUE(false, "Encoding error: destination type unknown");
break;
}
}
}
......
......@@ -48,6 +48,13 @@ static Platform getIGAInternalPlatform(TARGET_PLATFORM genxPlatform)
case GENX_BXT:
platform = Platform::GEN9;
break;
case GENX_CNL:
platform = Platform::GEN10;
break;
case GENX_ICL:
case GENX_ICLLP:
platform = Platform::GEN11;
break;
default:
break;
}
......@@ -128,6 +135,12 @@ iga::Op BinaryEncodingIGA::getIGAOp(G4_opcode op, G4_INST *inst) const
case G4_asr:
igaOp = iga::Op::ASR;
break;
case G4_ror:
igaOp = iga::Op::ROR;
break;
case G4_rol:
igaOp = iga::Op::ROL;
break;
case G4_cmp:
igaOp = iga::Op::CMP;
break;
......@@ -285,6 +298,9 @@ iga::Op BinaryEncodingIGA::getIGAOp(G4_opcode op, G4_INST *inst) const
case G4_dp2:
igaOp = iga::Op::DP2;
break;
case G4_dp4a:
igaOp = iga::Op::DP4A;
break;
case G4_line:
igaOp = iga::Op::LINE;
break;
......
......@@ -246,6 +246,24 @@ void CISA_IR_Builder::InitVisaWaTable(TARGET_PLATFORM platform, Stepping step)
VISA_WA_ENABLE(m_pWaTable, WaNoSimd16TernarySrc0Imm);
}
// WA for future platforms
if (platform == GENX_ICLLP || platform == GENX_ICL)
{
VISA_WA_ENABLE(m_pWaTable, Wa_1406306137);
}
if (platform == GENX_ICLLP && (step == Step_A || step == Step_B))
{
VISA_WA_ENABLE(m_pWaTable, Wa_2201674230);
}
switch (platform)
{
case GENX_ICLLP:
case GENX_ICL:
VISA_WA_ENABLE(m_pWaTable, Wa_1406950495);
break;
default:
break;
}
}
// note that this will break if we have more than one builder active,
......@@ -723,6 +741,9 @@ void CISA_IR_Builder::emitFCPatchFile()
case GENX_CHV: return cm::patch::PP_CHV;
case GENX_SKL: return cm::patch::PP_SKL;
case GENX_BXT: return cm::patch::PP_BXT;
case GENX_CNL: return cm::patch::PP_CNL;
case GENX_ICL: return cm::patch::PP_ICL;
case GENX_ICLLP: return cm::patch::PP_ICLLP;
default:
break;
}
......
......@@ -178,6 +178,12 @@ and|or|xor|shl|shr|asr {
return BINARY_LOGIC_OP;
}
rol|ror {
TRACE("\n** Binary Logic INST ");
CISAlval.opcode = str2opcode(yytext);
return BINARY_LOGIC_OP;
}
addc|subb {
TRACE("\n** MATH INST ");
......
......@@ -596,6 +596,41 @@ static uint32_t BDWCompactDataTypeTable[COMPACT_TABLE_SIZE]=
0x0004B248, //001001011001001001000
};
static uint32_t ICLCompactDataTypeTable[COMPACT_TABLE_SIZE] =
{
0x40001, // 001000000000000000001
0x40040, // 001000000000001000000
0x40041, // 001000000000001000001
0x400C1, // 001000000000011000001
0x40165, // 001000000000101100101
0x40BE5, // 001000000101111100101
0x40941, // 001000000100101000001
0x40945, // 001000000100101000101
0x40965, // 001000000100101100101
0x41041, // 001000001000001000001
0x43040, // 001000011000001000000
0x43041, // 001000011000001000001
0x45145, // 001000101000101000101
0x47144, // 001000111000101000100
0x47145, // 001000111000101000101
0x64965, // 001100100100101100101
0x65925, // 001100101100100100101
0x65964, // 001100101100101100100
0x65965, // 001100101100101100101
0x67964, // 001100111100101100100
0x0040C, // 000000000010000001100
0x40065, // 001000000000001100101
0x40145, // 001000000000101000101
0x41040, // 001000001000001000000
0x45144, // 001000101000101000100
0x47104, // 001000111000100000100
0x49209, // 001001001001000001001
0x6F965, // 001101111100101100101
0x67965, // 001100111100101100101
0x4F34C, // 001001111001101001100
0x49248, // 001001001001001001000
0x4B248, // 001001011001001001000
};
// ControlIndex Compact Instruction Field Mappings 3 Source Operands BDW/CHV
static uint32_t BDWCompactControlTable3Src[COMPACT_TABLE_SIZE_3SRC]=
......
......@@ -120,6 +120,8 @@ G4_opcode Get_G4_Opcode_From_Common_ISA_Opcode( ISA_Opcode opcode )
return G4_dp4;
case ISA_DPH:
return G4_dph;
case ISA_DP4A:
return G4_dp4a;
case ISA_EXP:
return G4_math;
case ISA_FRC:
......@@ -178,6 +180,10 @@ G4_opcode Get_G4_Opcode_From_Common_ISA_Opcode( ISA_Opcode opcode )
return G4_shr;
case ISA_ASR:
return G4_asr;
case ISA_ROL:
return G4_rol;
case ISA_ROR:
return G4_ror;
case ISA_BFE:
return G4_bfe;
case ISA_BFI:
......
......@@ -158,7 +158,7 @@ int Get_PreDefined_Surf_Index( int index );
inline bool isShiftOp(ISA_Opcode op)
{
return op == ISA_SHL || op == ISA_SHR || op == ISA_ASR;
return op == ISA_SHL || op == ISA_SHR || op == ISA_ASR || op == ISA_ROL || op == ISA_ROR;
}
......
......@@ -3964,6 +3964,10 @@ static iga_gen_t getIGAPlatform()
case GENX_CNL:
platform = IGA_GEN10;
break;
case GENX_ICL:
case GENX_ICLLP:
platform = IGA_GEN11;
break;
default:
break;
}
......
......@@ -103,6 +103,8 @@ HANDLE_INST( shl, 2, 1, InstTypeArith, GENX_BDW, \
HANDLE_INST( asr, 2, 1, InstTypeArith, GENX_BDW, \
ATTR_NONE )
HANDLE_INST( ror, 2, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
HANDLE_INST( rol, 2, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
HANDLE_INST( math, 2, 1, InstTypeArith, GENX_BDW, \
ATTR_NONE )
......@@ -132,7 +134,8 @@ HANDLE_INST( addc, 2, 1, InstTypeArith, GENX_BDW, \
ATTR_NONE )
HANDLE_INST( subb, 2, 1, InstTypeArith, GENX_BDW, \
ATTR_NONE )
HANDLE_INST( dp4a, 3, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
HANDLE_INST( madm , 3, 1, InstTypeArith, GENX_BDW, \
ATTR_NONE )
......
......@@ -7011,6 +7011,9 @@ bool G4_INST::canSupportSaturate() const
case G4_not:
case G4_or:
case G4_xor:
case G4_rol:
case G4_ror:
case G4_dp4a:
case G4_smov:
return false;
default:
......@@ -7065,6 +7068,7 @@ bool G4_INST::canSupportCondMod(const IR_Builder& builder) const
(op == G4_dp3) ||
(op == G4_dp4) ||
(op == G4_dph) ||
(op == G4_dp4a) ||
(op == G4_line) ||
(op == G4_lrp) ||
(op == G4_lzd) ||
......@@ -7572,6 +7576,8 @@ bool G4_INST::canDstBeAcc(const IR_Builder& builder) const
case G4_mad:
case G4_csel:
return builder.canMadHaveAcc();
case G4_dp4a:
return builder.relaxedACCRestrictions2();
default:
return false;
}
......@@ -7711,6 +7717,8 @@ bool G4_INST::canSrcBeAcc(int srcId, const IR_Builder& builder) const
return src->getModifier() == Mod_src_undef;
case G4_pln:
return builder.doPlane() && src->getModifier() == Mod_src_undef;
case G4_dp4a:
return builder.relaxedACCRestrictions2();
default:
return false;
}
......
#pragma once
// HW Capabilities for open source branch (currently Gen9 and below)
// HW Capabilities
// this are part of IR_Builder class and include in Build_IR.h
enum class PlatformGen
......@@ -7,7 +7,8 @@
GEN_UNKNOWN = 0,
GEN8 = 8,
GEN9 = 9,
GEN10 = 10
GEN10 = 10,
GEN11 = 11
};
PlatformGen getPlatformGeneration(TARGET_PLATFORM platform) const
......@@ -22,6 +23,9 @@
return PlatformGen::GEN9;
case GENX_CNL:
return PlatformGen::GEN10;
case GENX_ICL:
case GENX_ICLLP:
return PlatformGen::GEN11;
default:
assert(false && "unsupported platform");
return PlatformGen::GEN_UNKNOWN;
......@@ -30,7 +34,9 @@
bool hasMixMode() const
{
return (getGenxPlatform() > GENX_BDW && !getOption(vISA_DisableMixMode));
return getOption(vISA_ForceMixMode) ||
(getGenxPlatform() > GENX_BDW &&
getPlatformGeneration(getGenxPlatform()) != PlatformGen::GEN11 && !getOption(vISA_DisableMixMode));
}
bool canDoSLMSpill() const
......@@ -42,12 +48,12 @@
bool forceSamplerHeader() const
{
return m_options->getOption(vISA_forceSamplerHeader) ||
m_options->getOption(vISA_enablePreemption);
(getGenxPlatform() < GENX_ICL && m_options->getOption(vISA_enablePreemption));
}
bool needsNoPreemptR2ForSend() const
{
return false;
return getPlatformGeneration(getGenxPlatform()) == PlatformGen::GEN11;
}
bool noDDAllowedPlatform() const
......@@ -62,17 +68,17 @@
bool no64bitType() const
{
return false;
return getGenxPlatform() == GENX_ICLLP;
}
bool doPlane() const
{
return !getOption(vISA_expandPlane);
return getGenxPlatform() < GENX_ICL && !getOption(vISA_expandPlane);
}
bool favorFloatMov() const
{
return false;
return getGenxPlatform() >= GENX_ICL;
}
bool noScalarJmp() const
......@@ -107,17 +113,18 @@
bool noSrc2Regioning() const
{
return false;
return getGenxPlatform() >= GENX_ICL;
}
bool no64bitRegioning() const
{
return getGenxPlatform() == GENX_CHV || getGenxPlatform() == GENX_BXT;
return getGenxPlatform() == GENX_CHV || getGenxPlatform() == GENX_BXT ||
getGenxPlatform() == GENX_ICLLP;
}
bool noSrc1Byte() const
{
return getOption(vISA_noSrc1Byte);
return getOption(vISA_noSrc1Byte) || getGenxPlatform() >= GENX_ICL;
}
bool needsFenceCommitEnable() const
......@@ -134,7 +141,7 @@
bool hasIEEEDivSqrt() const
{
return true;
return getGenxPlatform() < GENX_ICL;
}
bool gotoJumpOnTrue() const
......@@ -146,10 +153,10 @@
{
return getGenxPlatform() < GENX_CNL;
}
bool hasSLMFence() const
{
return false;
return getGenxPlatform() >= GENX_ICL;
}
bool GRFAlign() const
......@@ -164,7 +171,7 @@
bool oneGRFBankDivision() const
{
return true;
return getGenxPlatform() != GENX_ICL;
}
bool lowHighBundle() const
......@@ -184,17 +191,17 @@
bool useNewR0Format() const
{
return false;
return getGenxPlatform() >= GENX_ICL;
}
int getPredMaskEnableBit() const
{
return 30;
return getGenxPlatform() < GENX_ICL ? 30 : 23;
}
int getBarrierIDMask() const
{
return 0x8F000000;
return getGenxPlatform() < GENX_ICL ? 0x8F000000 : 0x7F000000;
}
uint32_t getMaxSendMessageLength() const
......@@ -234,7 +241,7 @@
bool hasHeaderlessMRTWrite() const
{
return false;
return getGenxPlatform() >= GENX_ICLLP;
}
bool hasDotProductInst() const
......@@ -244,12 +251,12 @@
bool hasLRP() const
{
return true;
return getGenxPlatform() < GENX_ICL;
}
bool hasMadm() const
{
return true;
return getGenxPlatform() != GENX_ICLLP;
}
int getBarrierMask(bool enableBarrierInstCounterBits) const
......@@ -259,11 +266,16 @@
//pre-SKL: and (8) H0.0:ud r0.2:ud 0x0F000000 (r0.2, bit 24-27)
return enableBarrierInstCounterBits ? 0x0F00FE00 : 0x0F000000;
}
else
else if (getGenxPlatform() < GENX_ICL)
{
//SKL+: and (8) H0.0:ud r0.2:ud 0x8F000000 (r0.2, bit24-27, bit31)
return enableBarrierInstCounterBits ? 0x8F00FE00 : 0x8F000000;
}
else
{
//else: and (8) H0.0:ud r0.2:ud 0x7F000000 (r0.2, bit24-30)
return enableBarrierInstCounterBits ? 0x7F00FF00 : 0x7F000000;
}
}
bool canMadHaveAcc() const
......@@ -278,7 +290,7 @@
bool hasFdivPowWA() const
{
return true;
return getGenxPlatform() < GENX_ICL;
}
bool hasCondModForTernary() const
......@@ -303,14 +315,14 @@
}
bool doAccSub() const
{
return false;
}
{
return getPlatformGeneration(getGenxPlatform()) >= PlatformGen::GEN11;
}
bool hasNFType() const
{
return false;
}
{
return getGenxPlatform() >= GENX_ICL;
}
void getSSIDBits(uint32_t& width, uint32_t& start) const
{
......@@ -327,14 +339,15 @@
}
bool encodeAccRegSelAsAlign1() const
{
return false;
}
{
return getGenxPlatform() >= GENX_ICL;
}
bool fuseTypedWrites() const
{
return getOption(vISA_FuseTypedWrites);
}
{
return getOption(vISA_FuseTypedWrites) ||
getPlatformGeneration(getGenxPlatform()) == PlatformGen::GEN11;
}
bool hasSIMD16TypedRW() const
{
......
......@@ -1462,6 +1462,49 @@ bool HWConformity::fixMov(INST_LIST_ITER i, G4_BB* bb)
return false;
}
bool HWConformity::fixRotate(INST_LIST_ITER i, G4_BB* bb)
{
// rotate requires src0 and dst to have the same datatype precision
// It also does not support *B/*Q types, but that should be enforced at the vISA level
// returns true if new instruction is inserted
bool changed = false;
G4_INST* inst = *i;
if (inst->opcode() != G4_rol && inst->opcode() != G4_ror)
{
return false;
}
G4_DstRegRegion* dst = inst->getDst();
G4_SrcRegRegion* src = inst->getSrc(0)->asSrcRegRegion();
MUST_BE_TRUE(IS_WTYPE(dst->getType()) || IS_DTYPE(dst->getType()), "dst type must be *W or *D");
MUST_BE_TRUE(IS_WTYPE(src->getType()) || IS_DTYPE(src->getType()), "src type must be *W or *D");
if (G4_Type_Table[dst->getType()].byteSize != G4_Type_Table[src->getType()].byteSize)
{
// keep exec type same and change dst to be same type as src
inst->setDest(insertMovAfter(i, dst, src->getType(), bb));
changed = true;
}
if (dst->getType() == Type_W)
{
dst->setType(Type_UW);
}
else if (dst->getType() == Type_D)
{
dst->setType(Type_UD);
}
if (src->getType() == Type_W)
{
src->setType(Type_UW);
}
else if (src->getType() == Type_D)
{
src->setType(Type_UD);
}
return changed;
}
bool HWConformity::fixDstAlignment( INST_LIST_ITER i, G4_BB* bb, G4_Type extype, unsigned int dst_elsize )
{
......@@ -5927,6 +5970,7 @@ void HWConformity::conformBB( BB_LIST_ITER it)
}
fixLine(i, bb);
fixRotate(i, bb);
// CHV/BXT specific checks for 64b datatypes
fix64bInst( i, bb);
......
......@@ -150,7 +150,7 @@ namespace vISA
bool fixAddcSubb(G4_BB* bb);
void fixDataLayout();
bool fixMov(INST_LIST_ITER i, G4_BB* bb);
bool fixRotate(INST_LIST_ITER i, G4_BB* bb);
void helperGenerateTempDst(
G4_BB *bb,
......
......@@ -44,6 +44,8 @@ typedef enum tagEU_OPCODE {
EU_OPCODE_SHL = 0x9,
EU_OPCODE_SMOV = 0xA,
EU_OPCODE_ASR = 0xC,
EU_OPCODE_ROR = 0xE, // ICL+
EU_OPCODE_ROL = 0xF, // ICL+
EU_OPCODE_CMP = 0x10,
EU_OPCODE_CMPN = 0x11,
EU_OPCODE_CSEL = 0x12,
......@@ -94,6 +96,7 @@ typedef enum tagEU_OPCODE {
EU_OPCODE_DPH = 0x55,
EU_OPCODE_DP3 = 0x56,
EU_OPCODE_DP2 = 0x57,
EU_OPCODE_DP4A = 0x58,
EU_OPCODE_LINE = 0x59,
EU_OPCODE_PLN = 0x5A,
EU_OPCODE_MAD = 0x5B,
......
/*===================== begin_copyright_notice ==================================
Copyright (c) 2017 Intel Corporation
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
======================= end_copyright_notice ==================================*/
#if !defined(__IGFXHWEUISAICL_H__)
#define __IGFXHWEUISAICL_H__
namespace G11HDL
{
typedef enum tagDSTTYPE {
DSTTYPE_UD = 0x0, // Unsigned Doubleword integer
DSTTYPE_D = 0x1, // signed Doubleword integer
DSTTYPE_UW = 0x2, // Unsigned Word integer
DSTTYPE_W = 0x3, // signed Word integer
DSTTYPE_UB = 0x4, // Unsigned Byte integer
DSTTYPE_B = 0x5, // signed Byte integer
DSTTYPE_UQ = 0x6, // Unsigned Quadword integer
DSTTYPE_Q = 0x7, // signed Quadword integer
DSTTYPE_HF = 0x8, // Half Float (16-bit)
DSTTYPE_F = 0x9, // single precision Float (32-bit)
DSTTYPE_DF = 0xA, // Double precision Float (64-bit)
} DSTTYPE;
typedef enum tagSRCTYPE {
SRCTYPE_UD = 0x0, // Unsigned Doubleword
SRCTYPE_D = 0x1, // signed Doubleword
SRCTYPE_UW = 0x2, // Unsigned Word integer
SRCTYPE_W = 0x3, // signed Word integer
SRCTYPE_UB = 0x4, // unsigned Byte integer
SRCTYPE_B = 0x5, // signed Byte integer
SRCTYPE_UQ = 0x6, // Unsigned Quadword integer
SRCTYPE_Q = 0x7, // signed Quadword integer
SRCTYPE_HF = 0x8, // Half Float (16-bit)
SRCTYPE_F = 0x9, // single precision Float (32-bit)
SRCTYPE_DF = 0xA, // Double precision Float (64-bit)
} SRCTYPE;
typedef enum tagSRCIMMTYPE {
SRCIMMTYPE_UD = 0x0, // Unsigned Doubleword
SRCIMMTYPE_D = 0x1, // signed Doubleword
SR