Commit 89e1dea9 authored by Chen, Weiyu's avatar Chen, Weiyu Committed by gbsbuild

Remove unused vISA messages (gather4/scatter4/scatter_atomic/transpose_ld

Change-Id: Ib87f1e61e366a33a202dc1bc8749c8f94838292e
parent a4f261be
......@@ -2948,54 +2948,6 @@ void CEncoder::ScatterGather(ISA_Opcode opcode, CVariable* srcdst, CVariable* bu
dstVar));
}
void CEncoder::ScatterGather4(ISA_Opcode opcode, CVariable* srcdst, CVariable* bufId, CVariable* offset, CVariable* gOffset, e_predefSurface surface)
{
VISA_VectorOpnd* globalOffsetOpnd = nullptr;
if(gOffset)
{
globalOffsetOpnd = GetUniformSource(gOffset);
}
else
{
int value = 0;
V(vKernel->CreateVISAImmediate(globalOffsetOpnd, &value ,ISA_TYPE_UD));
}
VISA_RawOpnd* elementOffset = GetRawSource(offset);
VISA_StateOpndHandle* surfOpnd = GetVISASurfaceOpnd(surface, bufId);
VISA_RawOpnd* dstVar;
Common_VISA_EMask_Ctrl visaMask;
if(opcode == ISA_GATHER4)
{
dstVar = GetRawDestination(srcdst);
visaMask = GetAluEMask(srcdst);
}
else
{
dstVar = GetRawSource(srcdst);
visaMask = ConvertMaskToVisaType(m_encoderState.m_mask, m_encoderState.m_noMask);
}
uint nd = srcdst->GetSize();
if (m_encoderState.m_simdSize == SIMDMode::SIMD8)
nd = nd / SIZE_GRF;
else if (m_encoderState.m_simdSize == SIMDMode::SIMD16)
nd = nd / (SIZE_GRF * 2);
else
assert(0);
uint mask = BIT(nd)-1;
V(vKernel->AppendVISASurfAccessGather4Scatter4Inst(
opcode,
ConvertChannelMaskToVisaType(mask),
visaMask,
getExecSize(m_encoderState.m_simdSize),
surfOpnd,
globalOffsetOpnd,
elementOffset,
dstVar));
}
void CEncoder::GenericAlu(e_opcode opcode, CVariable* dst, CVariable* src0, CVariable* src1, CVariable* src2)
{
ISA_Opcode visaOpcode = ConvertOpcode[opcode];
......
......@@ -268,11 +268,9 @@ public:
inline void LoadMS(EOPCODE subOpcode, uint writeMask, CVariable* offset, const ResourceDescriptor& resource, uint numSources, CVariable* dst, llvm::SmallVector<CVariable*, 4>& payload, bool feedbackEnable);
inline void SetP(CVariable* dst, CVariable* src);
inline void Gather(CVariable* dst, CVariable* bufidx, CVariable* offset, CVariable* gOffset, e_predefSurface surface, int elementSize);
inline void Gather4(CVariable* dst, CVariable* bufidx, CVariable* offset, e_predefSurface surface);
inline void TypedRead4(const ResourceDescriptor& resource, CVariable* pU, CVariable* pV, CVariable* pR, CVariable* pLOD, CVariable* pDst, uint writeMask);
inline void TypedWrite4(const ResourceDescriptor& resource, CVariable* pU, CVariable* pV, CVariable* pR, CVariable* pLOD, CVariable* pSrc);
inline void Scatter(CVariable* val, CVariable* bufidx, CVariable* offset, CVariable* gOffset, e_predefSurface surface, int elementSize);
inline void Scatter4(CVariable* val, CVariable* bufIdx, CVariable* offset, CVariable* gOffset, e_predefSurface surface);
inline void IShr( CVariable* dst, CVariable* src0, CVariable* src1 );
inline void Min(CVariable* dst, CVariable* src0, CVariable* src1);
inline void Max(CVariable* dst, CVariable* src0, CVariable* src1);
......@@ -445,13 +443,6 @@ private:
CVariable* gOffset,
e_predefSurface surface,
int elementSize);
void ScatterGather4(
ISA_Opcode opcode,
CVariable* srcdst,
CVariable* bufId,
CVariable* offset,
CVariable* gOffset,
e_predefSurface surface);
void TypedReadWrite(
ISA_Opcode opcode,
const ResourceDescriptor& resource,
......@@ -751,11 +742,6 @@ inline void CEncoder::Gather(CVariable* dst, CVariable* bufId, CVariable* offset
ScatterGather(ISA_GATHER, dst, bufId, offset, gOffset, surface, elementSize);
}
inline void CEncoder::Gather4(CVariable* dst, CVariable* bufId, CVariable* offset, e_predefSurface surface)
{
ScatterGather4(ISA_GATHER4, dst, bufId, offset, nullptr, surface);
}
inline void CEncoder::TypedRead4(const ResourceDescriptor& resource, CVariable* pU, CVariable* pV,
CVariable* pR, CVariable* pLOD, CVariable* pDst, uint writeMask)
{
......@@ -773,11 +759,6 @@ inline void CEncoder::Scatter(CVariable* val, CVariable* bufidx, CVariable* offs
ScatterGather(ISA_SCATTER, val, bufidx, offset, gOffset, surface, elementSize);
}
inline void CEncoder::Scatter4(CVariable* val, CVariable* bufIdx, CVariable* offset, CVariable* gOffset, e_predefSurface surface)
{
ScatterGather4(ISA_SCATTER4, val, bufIdx, offset, gOffset, surface);
}
inline void CEncoder::SendC(CVariable* dst, CVariable* src, uint exDesc, CVariable* messDescriptor)
{
Send(dst, src, exDesc, messDescriptor, true);
......
......@@ -36,10 +36,8 @@ DECLARE_CISA_OPCODE(EOPCODE_ROL, "rol",
DECLARE_CISA_OPCODE(EOPCODE_ROR, "ror", ISA_ROR)
DECLARE_CISA_OPCODE(EOPCODE_OWLOAD, "oword_ld_unaligned", ISA_OWORD_LD_UNALIGNED)
DECLARE_CISA_OPCODE(EOPCODE_GATHER, "gather", ISA_GATHER)
DECLARE_CISA_OPCODE(EOPCODE_GATHER4, "gather4", ISA_GATHER4)
DECLARE_CISA_OPCODE(EOPCODE_TYPED4_READ, "typed4_read", ISA_GATHER4_TYPED)
DECLARE_CISA_OPCODE(EOPCODE_SCATTER, "scatter", ISA_SCATTER)
DECLARE_CISA_OPCODE(EOPCODE_SCATTER4, "scatter4", ISA_SCATTER4)
DECLARE_CISA_OPCODE(EOPCODE_TYPED4_WRITE, "typed4_write", ISA_SCATTER4_TYPED)
DECLARE_CISA_OPCODE(EOPCODE_MULH, "mulh", ISA_MULH)
DECLARE_CISA_OPCODE(EOPCODE_MOD, "mod", ISA_MOD)
......@@ -52,4 +50,3 @@ DECLARE_CISA_OPCODE(EOPCODE_BARRIER, "barrier",
DECLARE_CISA_OPCODE(EOPCODE_BFI, "bfi", ISA_BFI)
DECLARE_CISA_OPCODE(EOPCODE_BFE, "bfe", ISA_BFE)
DECLARE_CISA_OPCODE(EOPCODE_BFREV, "bfrev", ISA_BFREV)
DECLARE_CISA_OPCODE(EOPCODE_SCATTER_ATOMIC, "scatter_atomic", ISA_SCATTER_ATOMIC)
......@@ -422,17 +422,6 @@ public:
VISA_opnd *raw_dst_src, //dst/src
int line_no);
bool CISA_create_scatter4_instruction(ISA_Opcode opcode,
ChannelMask ch_mask,
bool mod,
Common_VISA_EMask_Ctrl emask,
int elemNum,
char *surf_name,
VISA_opnd *g_off_opnd, //global_offset
VISA_opnd *offset_raw, //element_offset
VISA_opnd *raw_dst_src, //dst/src
int line_no);
bool CISA_create_scatter4_typed_instruction(ISA_Opcode opcode,
VISA_opnd *pred,
ChannelMask ch_mask,
......@@ -481,19 +470,6 @@ public:
VISA_opnd *src0,
int line_no);
bool CISA_create_atomic_instruction (ISA_Opcode opcode,
VISAAtomicOps sub_op,
bool is16Bit,
Common_VISA_EMask_Ctrl emask,
unsigned execSize,
char *surface_name,
VISA_opnd *g_off,
VISA_opnd *elem_opnd,
VISA_opnd *dst,
VISA_opnd *src0,
VISA_opnd *src1,
int line_no);
bool CISA_create_dword_atomic_instruction(VISA_opnd *pred,
VISAAtomicOps subOpc,
bool is16Bit,
......
......@@ -1852,37 +1852,6 @@ bool CISA_IR_Builder::CISA_create_scatter_instruction(ISA_Opcode opcode,
return true;
}
bool CISA_IR_Builder::CISA_create_scatter4_instruction(ISA_Opcode opcode,
ChannelMask ch_mask,
bool mod,
Common_VISA_EMask_Ctrl emask,
int elemNum,
char *surf_name,
VISA_opnd *global_offset, //global_offset
VISA_opnd *element_offset, //element_offset
VISA_opnd *raw_dst_src, //dst/src
int line_no)
{
VISA_SurfaceVar *surfaceVar = (VISA_SurfaceVar*)m_kernel->getDeclFromName(surf_name);
MUST_BE_TRUE1(surfaceVar != NULL, line_no, "Surface was not found");
VISA_StateOpndHandle * surface = NULL;
m_kernel->CreateVISAStateOperandHandle(surface, surfaceVar);
Common_ISA_Exec_Size executionSize = EXEC_SIZE_16;
if(elemNum == 16)
{
executionSize = EXEC_SIZE_16;
}
else if(elemNum == 8)
{
executionSize = EXEC_SIZE_8;
}
m_kernel->AppendVISASurfAccessGather4Scatter4Inst(opcode, ch_mask.getAPI(), emask, executionSize, surface, (VISA_VectorOpnd *)global_offset, (VISA_RawOpnd *)element_offset, (VISA_RawOpnd *)raw_dst_src);
return true;
}
bool CISA_IR_Builder::CISA_create_scatter4_typed_instruction(ISA_Opcode opcode,
VISA_opnd *pred,
ChannelMask ch_mask,
......@@ -2042,47 +2011,6 @@ bool CISA_IR_Builder::CISA_create_invtri_inst(VISA_opnd *pred,
return true;
}
bool CISA_IR_Builder::CISA_create_atomic_instruction (ISA_Opcode opcode,
VISAAtomicOps sub_op,
bool is16Bit,
Common_VISA_EMask_Ctrl emask,
unsigned execSize,
char *surface_name,
VISA_opnd *g_off,
VISA_opnd *elem_opnd,
VISA_opnd *dst,
VISA_opnd *src0,
VISA_opnd *src1,
int line_no)
{
VISA_SurfaceVar *surfaceVar = (VISA_SurfaceVar*)m_kernel->getDeclFromName(surface_name);
MUST_BE_TRUE1(surfaceVar != NULL, line_no, "Surface was not found");
VISA_StateOpndHandle * surface = NULL;
m_kernel->CreateVISAStateOperandHandle(surface, surfaceVar);
Common_ISA_Exec_Size executionSize = EXEC_SIZE_8;
MUST_BE_TRUE1(execSize == 8 || execSize == 16, line_no, "Unsupported number of elements for atomic instruction.");
if (execSize == 8)
{
executionSize = EXEC_SIZE_8;
}
else if (execSize == 16)
{
executionSize = EXEC_SIZE_16;
}
m_kernel->AppendVISASurfAccessDwordAtomicInst(
sub_op, is16Bit, emask, executionSize, surface,
(VISA_VectorOpnd *)g_off, (VISA_RawOpnd *)elem_opnd,
(VISA_RawOpnd *)src0, (VISA_RawOpnd *)src1, (VISA_RawOpnd *)dst);
return true;
}
bool CISA_IR_Builder::CISA_create_dword_atomic_instruction(VISA_opnd *pred,
VISAAtomicOps subOpc,
bool is16Bit,
......
......@@ -1990,18 +1990,6 @@ public:
G4_SrcRegRegion* eltOffOpnd,
G4_SrcRegRegion* srcOpnd );
int translateVISADwordAtomicInst(
VISAAtomicOps op,
bool is16Bit,
Common_VISA_EMask_Ctrl emask,
Common_ISA_Exec_Size executionSize,
G4_Operand* surface,
G4_Operand* gOffOpnd,
G4_SrcRegRegion* eltOffOpnd,
G4_SrcRegRegion* src0Opnd,
G4_SrcRegRegion* src1Opnd,
G4_DstRegRegion* dstOpnd);
int translateVISADwordAtomicInst(VISAAtomicOps subOpc,
bool is16Bit,
G4_Predicate *pred,
......@@ -2028,14 +2016,6 @@ public:
G4_SrcRegRegion *src1,
G4_DstRegRegion *dst);
int translateTransposeVISALoadInst(
G4_Operand* surface,
unsigned blockWidth,
unsigned blockHeight,
G4_Operand* xOffOpnd,
G4_Operand* yOffOpnd,
G4_DstRegRegion* dstOpnd );
int translateVISAGather4TypedInst(G4_Predicate *pred,
Common_VISA_EMask_Ctrl emask,
ChannelMask chMask,
......
......@@ -828,7 +828,6 @@ static void readInstructionDataportNG(unsigned& bytePos, const char* buf, ISA_Op
{
case ISA_MEDIA_ST:
case ISA_MEDIA_LD:
case ISA_TRANSPOSE_LD:
{
uint8_t modifier = (ISA_MEDIA_LD == opcode || ISA_MEDIA_ST == opcode) ? readPrimitiveOperandNG<uint8_t>(bytePos, buf) : 0;
uint8_t surface = readPrimitiveOperandNG<uint8_t>(bytePos, buf);
......@@ -842,10 +841,7 @@ static void readInstructionDataportNG(unsigned& bytePos, const char* buf, ISA_Op
VISA_StateOpndHandle* surfaceHnd = NULL;
kernelBuilder->CreateVISAStateOperandHandle(surfaceHnd, container.surfaceVarDecls[surface]);
if (ISA_MEDIA_LD == opcode || ISA_MEDIA_ST == opcode)
kernelBuilder->AppendVISASurfAccessMediaLoadStoreInst(opcode, (MEDIA_LD_mod)modifier, surfaceHnd, width, height, (VISA_VectorOpnd*)xoffset, (VISA_VectorOpnd*)yoffset, msg, (CISA_PLANE_ID)plane);
else
kernelBuilder->AppendVISASurfAccessTransposeLoadInst(surfaceHnd, width, height, (VISA_VectorOpnd*)xoffset, (VISA_VectorOpnd*)yoffset, msg);
kernelBuilder->AppendVISASurfAccessMediaLoadStoreInst(opcode, (MEDIA_LD_mod)modifier, surfaceHnd, width, height, (VISA_VectorOpnd*)xoffset, (VISA_VectorOpnd*)yoffset, msg, (CISA_PLANE_ID)plane);
break;
}
case ISA_OWORD_ST:
......@@ -869,12 +865,9 @@ static void readInstructionDataportNG(unsigned& bytePos, const char* buf, ISA_Op
}
case ISA_GATHER:
case ISA_SCATTER:
case ISA_GATHER4:
case ISA_SCATTER4:
{
uint8_t ch_mask = (ISA_SCATTER4 == opcode || ISA_GATHER4 == opcode) ? readPrimitiveOperandNG<uint8_t>(bytePos, buf) : 0;
uint8_t elt_size = (ISA_SCATTER == opcode || ISA_GATHER == opcode) ? readPrimitiveOperandNG<uint8_t>(bytePos, buf) : 0;
if (ISA_GATHER4 == opcode || ISA_GATHER == opcode)
if (ISA_GATHER == opcode)
{
readPrimitiveOperandNG<uint8_t>(bytePos, buf);
} // modifier
......@@ -909,42 +902,7 @@ static void readInstructionDataportNG(unsigned& bytePos, const char* buf, ISA_Op
emask = transformMask(container, num_elts >> 4);
if (ISA_SCATTER4 == opcode || ISA_GATHER4 == opcode)
kernelBuilderImpl->AppendVISASurfAccessGather4Scatter4Inst(opcode, ChannelMask::createAPIFromBinary(opcode, ch_mask), emask, esize, surfaceHnd, globalOffset, elementOffset, msg);
else
kernelBuilderImpl->AppendVISASurfAccessGatherScatterInst(opcode, emask, (GATHER_SCATTER_ELEMENT_SIZE)(elt_size & 0x3), esize, surfaceHnd, globalOffset, elementOffset, msg);
break;
}
case ISA_SCATTER_ATOMIC:
{
Common_VISA_EMask_Ctrl emask = vISA_EMASK_M1;
VISAAtomicOps op =
static_cast<VISAAtomicOps>(
readPrimitiveOperandNG<uint8_t>(bytePos, buf));
uint8_t num_elts = readPrimitiveOperandNG<uint8_t>(bytePos, buf);
uint8_t surface = readPrimitiveOperandNG<uint8_t>(bytePos, buf);
VISA_VectorOpnd* globalOffset = readVectorOperandNG(bytePos, buf, container, false);
VISA_RawOpnd* elementOffset = readRawOperandNG(bytePos, buf, container);
VISA_RawOpnd* src0 = readRawOperandNG(bytePos, buf, container);
VISA_RawOpnd* src1 = readRawOperandNG(bytePos, buf, container);
VISA_RawOpnd* dst = readRawOperandNG(bytePos, buf, container);
emask = transformMask(container, (num_elts >> 4) & 0xF);
num_elts = num_elts & 0x3;
if (num_elts == 0) num_elts = 8;
else if (num_elts == 1) num_elts = 16;
else
MUST_BE_TRUE(false, "Unsupported number of elements for ISA_DWORD_ATOMIC, must be 8 or 16.");
Common_ISA_Exec_Size esize = Get_Common_ISA_Exec_Size_From_Raw_Size(num_elts);
VISA_StateOpndHandle* surfaceHnd = NULL;
kernelBuilderImpl->CreateVISAStateOperandHandle(surfaceHnd, container.surfaceVarDecls[surface]);
kernelBuilderImpl->AppendVISASurfAccessDwordAtomicInst(
op, /*is16Bit*/ false, emask, esize, surfaceHnd, globalOffset,
elementOffset, src0, src1, dst);
kernelBuilderImpl->AppendVISASurfAccessGatherScatterInst(opcode, emask, (GATHER_SCATTER_ELEMENT_SIZE)(elt_size & 0x3), esize, surfaceHnd, globalOffset, elementOffset, msg);
break;
}
case ISA_GATHER4_TYPED:
......
......@@ -269,8 +269,8 @@ media_ld|media_st {
return MEDIA_OP;
}
gather|scatter|gather4|scatter4 {
TRACE("\n** gather/scatter/gather4/scatter4 INST ");
gather|scatter {
TRACE("\n** gather/scatter INST ");
CISAlval.opcode = str2opcode(yytext);
return SCATTER_OP;
}
......
......@@ -878,7 +878,6 @@ CISAInst: LogicInstruction
| Scatter4ScaledInstruction
| SynchronizationInstruction
| BranchInstruction
| UntypedAtomicInstruction
| DwordAtomicInstruction
| TypedAtomicInstruction
| SampleInstruction
......@@ -1061,12 +1060,6 @@ ScatterInstruction : SCATTER_OP ElemNum ExecSize OwordModifier VAR VecSrcOperand
{
pCisaBuilder->CISA_create_scatter_instruction($1, (int) $2, $3.emask, $3.exec_size, $4, $5, $6.cisa_gen_opnd, $7.cisa_gen_opnd, $8.cisa_gen_opnd, CISAlineno);
};
// 1 2 3 4 5 6 7 8
| SCATTER_OP SAMPLER_CHANNEL ExecSize OwordModifier VAR VecSrcOperand_G_I_IMM RawOperand RawOperand
{
pCisaBuilder->CISA_create_scatter4_instruction($1, ChannelMask::createFromAPI($2), (int)$4, $3.emask, (int)$3.exec_size, $5, $6.cisa_gen_opnd, $7.cisa_gen_opnd, $8.cisa_gen_opnd, CISAlineno);
};
// 1 2 3 4 5 6 7 8 9 10
ScatterTypedInstruction : Predicate SCATTER_TYPED_OP SAMPLER_CHANNEL ExecSize VAR RawOperand RawOperand RawOperand RawOperand RawOperand
{
......@@ -1098,12 +1091,6 @@ SynchronizationInstruction: BARRIER_OP
pCisaBuilder->CISA_create_sbarrier_instruction(false);
};
// 1 2 3 4 5 6 7 8 9 10
UntypedAtomicInstruction : ATOMIC_OP ATOMIC_SUB_OP IS_ATOMIC16 ExecSize VAR VecSrcOperand_G_I_IMM RawOperand RawOperand RawOperand RawOperand
{
pCisaBuilder->CISA_create_atomic_instruction(ISA_SCATTER_ATOMIC, $2, $3, $4.emask, $4.exec_size, $5, $6.cisa_gen_opnd, $7.cisa_gen_opnd, $8.cisa_gen_opnd, $9.cisa_gen_opnd, $10.cisa_gen_opnd, CISAlineno);
};
// 1 2 3 4 5 6 7 8 9 10
DwordAtomicInstruction: Predicate DWORD_ATOMIC_OP ATOMIC_SUB_OP IS_ATOMIC16 ExecSize VAR RawOperand RawOperand RawOperand RawOperand
{
......
......@@ -34,14 +34,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
const char * implictKindStrings[IMPLICIT_INPUT_COUNT] = { "EXPLICIT", "LOCAL_SIZE", "GROUP_COUNT", "LOCAL_ID" };
uint8_t Transpose_Read_Block_size[4] =
{
1,
2,
4,
8
};
const char* Rel_op_str[ISA_CMP_UNDEF + 1] =
{
"eq", // equal
......
......@@ -202,8 +202,6 @@ typedef enum {
NUM_REGION = 0x8
} Common_ISA_Region_Val;
extern uint8_t Transpose_Read_Block_size[4];
extern const char* Rel_op_str[ISA_CMP_UNDEF + 1];
extern const char* media_ld_mod_str[MEDIA_LD_Mod_NUM];
......@@ -884,13 +882,6 @@ private:
/// needReverseMaskForBinary - Channel mask needs reverse during vISA binary
/// encoding.
static bool needReverseMaskForBinary(ISA_Opcode opc) {
switch (opc) {
default:
break;
case ISA_GATHER4:
case ISA_SCATTER4:
return true;
}
return false;
}
......
......@@ -229,7 +229,6 @@ G4_opcode Get_G4_Opcode_From_Common_ISA_Opcode( ISA_Opcode opcode )
case ISA_MEDIA_ST:
case ISA_GATHER:
case ISA_SCATTER:
case ISA_SCATTER_ATOMIC:
case ISA_OWORD_LD_UNALIGNED:
case ISA_SAMPLE:
case ISA_SAMPLE_UNORM:
......
......@@ -96,11 +96,11 @@ struct ISA_Inst_Info ISA_Inst_Table[ISA_OPCODE_ENUM_SIZE] =
{ ISA_MEDIA_ST, ISA_Inst_Data_Port, "media_st", 6, 0 },
{ ISA_GATHER, ISA_Inst_Data_Port, "gather", 4, 1 },
{ ISA_SCATTER, ISA_Inst_Data_Port, "scatter", 5, 0 },
{ ISA_SCATTER_ATOMIC, ISA_Inst_Data_Port, "untyped_atomic", 6, 1 },
{ ISA_RESERVED_3B, ISA_Inst_Reserved, "reserved3b", 0, 0 },
{ ISA_OWORD_LD_UNALIGNED, ISA_Inst_Data_Port, "oword_ld_unaligned", 2, 1 },
{ ISA_GATHER4, ISA_Inst_Data_Port, "gather4", 4, 1 },
{ ISA_SCATTER4, ISA_Inst_Data_Port, "scatter4", 5, 0 },
{ ISA_TRANSPOSE_LD, ISA_Inst_Data_Port, "read_transpose", 5, 1 },
{ ISA_RESERVED_3D, ISA_Inst_Reserved, "reserved3d", 0, 0 },
{ ISA_RESERVED_3E, ISA_Inst_Reserved, "reserved3e", 0, 0 },
{ ISA_RESERVED_3F, ISA_Inst_Reserved, "reserved3f", 0, 0 },
{ ISA_SAMPLE, ISA_Inst_Sampler, "sample", 5, 1 },
{ ISA_SAMPLE_UNORM, ISA_Inst_Sampler, "sample_unorm", 6, 1 },
{ ISA_LOAD, ISA_Inst_Sampler, "load", 4, 1 },
......@@ -825,16 +825,8 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] =
},
/// 59
{ ALL, ISA_SCATTER_ATOMIC, ISA_Inst_Data_Port, "untyped_atomic", 8, 0,
{ ALL, ISA_RESERVED_3B, ISA_Inst_Reserved, "reserved_3B", 8, 0,
{
{OPND_ATOMIC_SUBOP, ISA_TYPE_UB, 0},
{OPND_ELEM_NUM, ISA_TYPE_UB, ELEM_NUM_8_16},
{OPND_SURFACE, ISA_TYPE_UB, 0},
{OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
{OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
{OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D, GRF_ALIGNED},
{OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D, GRF_ALIGNED},
{OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D, GRF_ALIGNED},
},
},
......@@ -852,43 +844,21 @@ VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE] =
},
/// 61
{ ALL, ISA_GATHER4, ISA_Inst_Data_Port, "gather4", 7, 0,
{ ALL, ISA_RESERVED_3D, ISA_Inst_Reserved, "reserved_3D", 0, 0,
{
{OPND_CHANNEL_SIMD_MODE, ISA_TYPE_UB, 0},
{OPND_IS_MODIFIED, ISA_TYPE_UB, 0},
{OPND_ELEM_NUM, ISA_TYPE_UB, 0},
{OPND_SURFACE, ISA_TYPE_UB, 0},
{OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION},
{OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
{OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D | ISA_TYPE_F, GRF_ALIGNED},
},
},
/// 62
{ ALL, ISA_SCATTER4, ISA_Inst_Data_Port, "scatter4", 6, 0,
{ ALL, ISA_RESERVED_3E, ISA_Inst_Reserved, "reserved_3E", 0, 0,
{
{OPND_CHANNEL_SIMD_MODE, ISA_TYPE_UB, 0},
{OPND_ELEM_NUM, ISA_TYPE_UB, 0},
{OPND_SURFACE, ISA_TYPE_UB, 0},
{OPND_VECTOR_SRC_G_I_IMM, ISA_TYPE_UD, SCALAR_REGION},
{OPND_RAW, ISA_TYPE_UD, GRF_ALIGNED},
{OPND_RAW, ISA_TYPE_UD | ISA_TYPE_D | ISA_TYPE_F, GRF_ALIGNED},
},
},
/// 63
{ ALL, ISA_TRANSPOSE_LD, ISA_Inst_Data_Port, "transpose_ld", 6, 0,
{ ALL, ISA_RESERVED_3F, ISA_Inst_Reserved, "reserved_3F", 0, 0,
{
{OPND_SURFACE, ISA_TYPE_UB, 0},
{OPND_BLOCK_WIDTH, ISA_TYPE_UB, VALUE_1_32},
{OPND_BLOCK_HEIGHT, ISA_TYPE_UB, VALUE_1_64},
{OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
{OPND_VECTOR_SRC_G_I_IMM_AO, ISA_TYPE_UD, SCALAR_REGION},
{OPND_RAW, 0, GRF_ALIGNED |SIZE_GE_WIDTH_M_HIEGH},
},
},
/// 64
......
......@@ -2053,7 +2053,6 @@ static string printInstructionDataport(const kernel_format_t* header, const CISA
{
case ISA_MEDIA_ST:
case ISA_MEDIA_LD:
case ISA_TRANSPOSE_LD:
{
uint8_t plane = 0;
uint8_t block_width = 0;
......@@ -2074,31 +2073,16 @@ static string printInstructionDataport(const kernel_format_t* header, const CISA
if (opcode == ISA_MEDIA_LD) sstr << "." << media_ld_mod_str[modifier];
if (opcode == ISA_MEDIA_ST) sstr << "." << media_st_mod_str[modifier];
if (opcode != ISA_TRANSPOSE_LD)
{
sstr << " (";
block_width = getPrimitiveOperand<uint8_t>(inst, i++);
sstr << (unsigned)block_width;
sstr << ",";
block_height = getPrimitiveOperand<uint8_t>(inst, i++);
sstr << (unsigned)block_height;
sstr << ")";
}
else
{
sstr << " (";
block_width = Transpose_Read_Block_size[getPrimitiveOperand<uint8_t>(inst, i++)];
sstr << (unsigned)block_width;
sstr << ",";
block_height = Transpose_Read_Block_size[getPrimitiveOperand<uint8_t>(inst, i++)];
sstr << (unsigned)block_height;
sstr << ")";
}
sstr << " (";
block_width = getPrimitiveOperand<uint8_t>(inst, i++);
sstr << (unsigned)block_width;
sstr << ",";
block_height = getPrimitiveOperand<uint8_t>(inst, i++);
sstr << (unsigned)block_height;
sstr << ")";
sstr << " T" << (unsigned)surface;
if (opcode != ISA_TRANSPOSE_LD)
sstr << " " << (unsigned)plane;
sstr << " " << (unsigned)plane;
/// x offset
sstr << printOperand(header, inst, i++, opt);
......@@ -2201,88 +2185,6 @@ static string printInstructionDataport(const kernel_format_t* header, const CISA
break;
}
case ISA_GATHER4:
case ISA_SCATTER4:
{
uint8_t ch_mask = 0;
uint8_t num_elts = 0;
ch_mask = getPrimitiveOperand<uint8_t>(inst, i++);
ch_mask = ch_mask & 0xF;
if (ISA_GATHER4 == opcode)
{
modifier = getPrimitiveOperand<uint8_t>(inst, i++);
}
num_elts = getPrimitiveOperand<uint8_t>(inst, i++);
// channel mask
sstr << "." << channel_mask_slm_str[ch_mask];
// num_elts
sstr << " " << printExecutionSizeForScatterGather(num_elts);
// modifier
if (ISA_GATHER4 == opcode && modifier & 0x1)
{
sstr << ".mod";
}
//surface
surface = getPrimitiveOperand<uint8_t>(inst, i++);
sstr <<printSurfaceIndex(surface);
/// global offset
sstr << printOperand(header, inst, i++, opt);
/// element offset
sstr << printOperand(header, inst, i++, opt);
/// message operand (src or dst)
sstr << printOperand(header, inst, i++, opt);
break;
}
case ISA_SCATTER_ATOMIC:
{
uint8_t num_elts = 0;
VISAAtomicOps op
= static_cast<VISAAtomicOps>(getPrimitiveOperand<uint8_t>(inst, i++));
/// TODO: Need platform information for this to work.
sstr << "." << CISAAtomicOpNames[op];
num_elts = getPrimitiveOperand<uint8_t>(inst, i++);
sstr << " " << printExecutionSizeForScatterGather(num_elts);
surface = getPrimitiveOperand<uint8_t>(inst, i++);
sstr <<printSurfaceIndex(surface);
/// global offset
sstr << printOperand(header, inst, i++, opt);
/// element offset
sstr << printOperand(header, inst, i++, opt);
/// DWORD_ATOMIC is wierd and has the text version
/// putting the dst operand before the src operands.
stringstream sstr1;
/// src0
sstr1 << printOperand(header, inst, i++, opt);
/// src1
sstr1 << printOperand(header, inst, i++, opt);
/// message operand (src or dst)
sstr << printOperand(header, inst, i++, opt);
sstr << sstr1.str();
break;
}
case ISA_GATHER4_TYPED:
case ISA_SCATTER4_TYPED:
{
......
......@@ -2457,7 +2457,6 @@ static void verifyInstructionDataport(const common_isa_header& isaHeader, const
{
case ISA_MEDIA_ST:
case ISA_MEDIA_LD:
case ISA_TRANSPOSE_LD:
{
uint8_t plane = 0;
uint8_t block_width = 0;
......@@ -2477,7 +2476,7 @@ static void verifyInstructionDataport(const common_isa_header& isaHeader, const
}
surface = getPrimitiveOperand<uint8_t>(inst, i++);
REPORT_INSTRUCTION(options,0 != surface, "Surface T0 (the SLM surface) is not allowed for MEDIA_LD/MEDIA_ST/TRANSPOSE_LD");
REPORT_INSTRUCTION(options,0 != surface, "Surface T0 (the SLM surface) is not allowed for MEDIA_LD/MEDIA_ST");
REPORT_INSTRUCTION(options,surface < numPreDefinedSurfs + header->surface_count,
"CISA dataport instruction uses an undeclared surface.");
......@@ -2500,16 +2499,6 @@ static void verifyInstructionDataport(const common_isa_header& isaHeader, const
"MEDIA_LD/MEDIA_ST block height must be in the range [1, 64]: %d",
block_height);
}
else if (ISA_TRANSPOSE_LD == opcode)
{
REPORT_INSTRUCTION(options,block_width <= 3,
"TRANSPOSE_LD block width must be in the range [0, 3]: %d",
block_width);
REPORT_INSTRUCTION(options,block_height <= 3,
"TRANSPOSE_LD block height must be in the range [0, 3]: %d",
block_height);
}
if (ISA_MEDIA_LD == opcode)
{
......@@ -2535,10 +2524,6 @@ static void verifyInstructionDataport(const common_isa_header& isaHeader, const
"transaction where block width <= 64 bytes and size <= 256 bytes. "
"Block width: %d. Block height: %d", block_width, block_height);
}
else if (ISA_TRANSPOSE_LD == opcode)
{
/// Information lost from CISA emission, can't verify here.
}
Common_ISA_Operand_Class operand_class_xoff = getVectorOperand(inst, i++).getOperandClass();
REPORT_INSTRUCTION(options,operand_class_xoff != OPERAND_ADDRESS && operand_class_xoff != OPERAND_PREDICATE,
......@@ -2580,113 +2565,11 @@ static void verifyInstructionDataport(const common_isa_header& isaHeader, const