Commit 95bf0d08 authored by Diana Chen's avatar Diana Chen Committed by gbsbuild

Add G4_InstOption::NoCompact.

And in VISAKernelImpl::expandIndirectCallWithRegTarget, set the
inserted add instructions to NoCompact so that the calculated IP
based offset is correct

Change-Id: Ie1c9d34e29ea7231b5e23ea8cf52006d37a27684
parent 3273da82
......@@ -395,19 +395,19 @@ inline uint32_t GetOperandSrcType(G4_Operand *src)
type = regType;
break;
case Type_DF:
type = SRC_TYPE_DF;
type = SRC_TYPE_DF;
break;
case Type_F:
type = SRC_TYPE_F;
type = SRC_TYPE_F;
break;
case Type_UQ:
type = SRC_TYPE_UQ;
type = SRC_TYPE_UQ;
break;
case Type_Q:
type = SRC_TYPE_Q;
type = SRC_TYPE_Q;
break;
case Type_HF:
type = SRC_TYPE_HF;
type = SRC_TYPE_HF;
break;
default:
type = SRC_TYPE_UNDEF;
......@@ -419,7 +419,7 @@ inline uint32_t GetOperandSrcType(G4_Operand *src)
inline uint32_t GetOperandSrcImmType(G4_Operand *src)
{
uint32_t type;
switch (src->getType()) {
switch (src->getType()) {
case Type_UD:
case Type_D:
case Type_UW:
......@@ -427,25 +427,25 @@ inline uint32_t GetOperandSrcImmType(G4_Operand *src)
type = src->getType();
break;
case Type_UV:
type = SRC_IMM_TYPE_UV;
type = SRC_IMM_TYPE_UV;
break;
case Type_VF:
type = SRC_IMM_TYPE_VF;
type = SRC_IMM_TYPE_VF;
break;
case Type_V:
type = SRC_IMM_TYPE_V;
type = SRC_IMM_TYPE_V;
break;
case Type_F:
type = SRC_IMM_TYPE_F;
type = SRC_IMM_TYPE_F;
break;
case Type_UQ:
type = SRC_IMM_TYPE_UQ;
type = SRC_IMM_TYPE_UQ;
break;
case Type_Q:
type = SRC_IMM_TYPE_Q;
type = SRC_IMM_TYPE_Q;
break;
case Type_DF:
type = SRC_IMM_TYPE_DF;
type = SRC_IMM_TYPE_DF;
break;
case Type_HF:
type = SRC_IMM_TYPE_HF;
......@@ -616,20 +616,20 @@ inline void SetOperandDstType(BinInst *mybin, G4_DstRegRegion *dst)
case Type_UW:
case Type_W:
case Type_UB:
case Type_B:
case Type_B:
SetDstType(mybin, regType);
break;
case Type_DF:
SetDstType(mybin, DST_TYPE_DF);
SetDstType(mybin, DST_TYPE_DF);
break;
case Type_F:
SetDstType(mybin, DST_TYPE_F);
SetDstType(mybin, DST_TYPE_F);
break;
case Type_UQ:
SetDstType(mybin, DST_TYPE_UQ);
SetDstType(mybin, DST_TYPE_UQ);
break;
case Type_Q:
SetDstType(mybin, DST_TYPE_Q);
SetDstType(mybin, DST_TYPE_Q);
break;
case Type_HF:
SetDstType(mybin, DST_TYPE_HF);
......@@ -2911,7 +2911,9 @@ inline BinaryEncoding::Status BinaryEncoding::ProduceBinaryInstructions()
if (doCompaction())
{
// do not compact the instruction that mark as NoCompact
inst->getBinInst()->SetMustCompactFlag(false);
inst->getBinInst()->SetDontCompactFlag(inst->isNoCompactedInst());
/**
* handling switch/case for gen6: jump table should not be compacted
......@@ -3190,7 +3192,7 @@ bool BinaryEncoding::EncodeConditionalBranches(G4_INST *inst,
}
if ( op == G4_call && inst->getSrc(0))
{
{
if (inst->getSrc(0)->isLabel())
{
......
......@@ -136,7 +136,7 @@ static inline int GetOperandSrcHDLImmType(G4_Type srcType)
int type = G9HDL::SRCIMMTYPE_UD;
if (getGenxPlatform() == GENX_CNL)
{
switch (srcType) {
switch (srcType) {
case Type_UD: type = G9HDL::SRCIMMTYPE_UD; break;
case Type_D: type = G9HDL::SRCIMMTYPE_D; break;
case Type_UW: type = G9HDL::SRCIMMTYPE_UW; break;
......@@ -154,7 +154,7 @@ static inline int GetOperandSrcHDLImmType(G4_Type srcType)
}
else
{
switch (srcType) {
switch (srcType) {
case Type_UD: type = G11HDL::SRCIMMTYPE_UD; break;
case Type_D: type = G11HDL::SRCIMMTYPE_D; break;
case Type_UW: type = G11HDL::SRCIMMTYPE_UW; break;
......@@ -864,7 +864,7 @@ inline void BinaryEncodingCNL::EncodeOneSrcInst(G4_INST* inst, G9HDL::EU_INSTRUC
else
{
SrcBuilder<G9HDL::EU_INSTRUCTION_SOURCES_REG,0>::EncodeEuInstructionSourcesReg(
inst, src0, oneSrc. GetRegsource() //by reference
inst, src0, oneSrc. GetRegsource() //by reference
);
}
......@@ -2237,13 +2237,13 @@ BinaryEncodingCNL::Status BinaryEncodingCNL::DoAllEncodingCALL(G4_INST* inst)
}
}
else
{
{
//Needed for correctness
oneSrc.SetSrc1Regfile(G9HDL::REGFILE_IMM);
oneSrc.SetSrc1Srctype(GetOperandSrcHDLImmType(Type_D));
}
bin->DWords[0] = oneSrc.GetDWORD(0);
......@@ -2483,7 +2483,7 @@ void BinaryEncodingCNL::DoAll()
BDWCompactSubRegTable.AddIndex1(IVBCompactSubRegTable[i] & 0x1F, i);
BDWCompactSubRegTable.AddIndex2(IVBCompactSubRegTable[i] & 0x3FF, i);
if (getGenxPlatform() > GENX_CNL)
{
{
BDWCompactDataTypeTableStr.AddIndex(ICLCompactDataTypeTable[i], i);
}
else
......@@ -2538,6 +2538,8 @@ void BinaryEncodingCNL::DoAll()
if (doCompaction())
{
inst->getBinInst()->SetMustCompactFlag(false);
inst->getBinInst()->SetDontCompactFlag(inst->isNoCompactedInst());
/**
* handling switch/case for gen6: jump table should not be compacted
*/
......
......@@ -374,6 +374,10 @@ private:
options.add(iga::InstOpt::NOSRCDEPSET);
}
}
if (inst->isNoCompactedInst())
{
options.add(iga::InstOpt::NOCOMPACT);
}
return options;
}
......
......@@ -33,7 +33,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define G4_DEFAULT_GRF_NUM 128
#define UNDEFINED_VAL 0xFFFFFFFF
#define UNDEFINED_SHORT 0x8000
#define UNDEFINED_SHORT 0x8000
#define UNDEFINED_EXEC_SIZE 0xFF
#define G4_BSIZE 1 // 1 byte 8 bits
......@@ -65,7 +65,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define G4_MAX_ADDR_IMM 511
#define G4_MIN_ADDR_IMM -512
#define IVB_MSG_TYPE_OFFSET 14
#define IVB_MSG_TYPE_OFFSET 14
#define MSG_BLOCK_SIZE_OFFSET 8
#define MSG_BLOCK_NUMBER_OFFSET 10
#define MAX_SEND_RESP_LEN 8
......@@ -80,7 +80,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STRINGIFY(X) #X,
/*
* For Gen6, only the following instructions can have
* For Gen6, only the following instructions can have
* interger sources and float destination:
* MOV, ADD, MUL, MAC, MAD, LINE
*/
......@@ -147,16 +147,16 @@ enum G4_Align
Odd = 3, // old align
Even2GRF = 4, // 2GRF even align 1100
Odd2GRF = 5, // 2GRF old align, 0011
Align_NUM = 6 // Num of alignment
Align_NUM = 6 // Num of alignment
};
// To support sub register alignment
enum G4_SubReg_Align
{
Any = 1,
Even_Word = 2,
Any = 1,
Even_Word = 2,
Four_Word = 4,
Eight_Word = 8,
Eight_Word = 8,
Sixteen_Word = 16, // one register align
};
......@@ -167,7 +167,7 @@ enum G4_SrcModifier
Mod_Abs, // (abs), absolute value
Mod_Minus_Abs, // -(abs)
Mod_Not, // invert (for BDW logic instruction)
Mod_src_undef // undefined
Mod_src_undef // undefined
};
enum G4_CondModifier
......@@ -192,7 +192,7 @@ enum G4_PredState
PredState_Minus, // -
PredState_undef // undefined
};
enum G4_RegAccess {
Direct,
IndirGRF,
......@@ -202,32 +202,32 @@ enum G4_RegAccess {
// register and Imm data type
// Note: Check G4_Type_ByteFootprint if this is modified
//
enum G4_Type
enum G4_Type
{
Type_UD = 0,// unsigned double word integer
Type_UD = 0,// unsigned double word integer
Type_D, // signed double word integer
Type_UW, // unsigned word integer
Type_W, // signed word integer
Type_UW, // unsigned word integer
Type_W, // signed word integer
Type_UB, // unsigned byte integer
Type_B, // signed byte integer
Type_F, // signed single precision
Type_VF, // 32-bit restricted Vector Float
Type_B, // signed byte integer
Type_F, // signed single precision
Type_VF, // 32-bit restricted Vector Float
Type_V, // 32-bit halfbyte integer Vector
Type_DF,
Type_BOOL,
Type_UV,
Type_Q, // 64-bit signed integer
Type_UQ, // 64-bit unsigned integer
Type_UQ, // 64-bit unsigned integer
Type_HF, // half float
Type_NF, // native float (only used by plane macro)
Type_UNDEF
};
typedef struct
typedef struct
{
G4_Type type;
unsigned int bitSize;
unsigned int byteSize;
unsigned int byteSize;
unsigned short footprint; // bit pattern that corresponds to type's byte usage
const char* str; //constant string representation of the type
} G4_Type_Info;
......@@ -248,50 +248,51 @@ enum G4_InstType
InstTypeReserved // reserved (unused)
};
enum G4_RegFileKind
enum G4_RegFileKind
{
G4_UndefinedRF = 0x0,
G4_GRF = 0x1, // general register file
G4_ADDRESS = 0x2, // architectural register file
G4_INPUT = 0x4, // input payload register
G4_INPUT = 0x4, // input payload register
G4_FLAG = 0x20,
};
//
//
// multiple options can coexist so we define one bit for each option
//
enum G4_InstOption
{
InstOpt_NoOpt = 0x0,
InstOpt_Align16 = 0x00000002,
InstOpt_NoOpt = 0x0,
InstOpt_Align16 = 0x00000002,
InstOpt_M0 = 0x00100000,
InstOpt_M4 = 0x00200000,
InstOpt_M8 = 0x00400000,
InstOpt_M12 = 0x00800000,
InstOpt_M16 = 0x01000000,
InstOpt_M20 = 0x02000000,
InstOpt_M24 = 0x04000000,
InstOpt_M28 = 0x08000000,
InstOpt_Switch = 0x00000010,
InstOpt_Atomic = 0x00000020,
InstOpt_NoDDChk = 0x00000040,
InstOpt_NoDDClr = 0x00000080,
InstOpt_WriteEnable = 0x00000100,
InstOpt_BreakPoint = 0x00000200,
InstOpt_EOT = 0x00000400,
InstOpt_M12 = 0x00800000,
InstOpt_M16 = 0x01000000,
InstOpt_M20 = 0x02000000,
InstOpt_M24 = 0x04000000,
InstOpt_M28 = 0x08000000,
InstOpt_Switch = 0x00000010,
InstOpt_Atomic = 0x00000020,
InstOpt_NoDDChk = 0x00000040,
InstOpt_NoDDClr = 0x00000080,
InstOpt_WriteEnable = 0x00000100,
InstOpt_BreakPoint = 0x00000200,
InstOpt_EOT = 0x00000400,
InstOpt_AccWrCtrl = 0x00000800,
InstOpt_Compacted = 0x00002000,
InstOpt_Compacted = 0x00002000,
InstOpt_NoCompact = 0x00001000,
InstOpt_NoSrcDepSet = 0x00004000,
InstOpt_NoPreempt = 0x00008000,
InstOpt_NoPreempt = 0x00008000,
InstOpt_END = 0xFFFFFFFF
InstOpt_END = 0xFFFFFFFF
};
#define InstOpt_QuarterMasks \
(InstOpt_M0 | InstOpt_M4 | InstOpt_M8 | InstOpt_M12 | InstOpt_M16 | InstOpt_M20 | InstOpt_M24 | InstOpt_M28)
(InstOpt_M0 | InstOpt_M4 | InstOpt_M8 | InstOpt_M12 | InstOpt_M16 | InstOpt_M20 | InstOpt_M24 | InstOpt_M28)
#define InstOpt_Masks (InstOpt_QuarterMasks | InstOpt_WriteEnable)
typedef struct _G4_InstOptInfo
......@@ -389,7 +390,7 @@ enum G4_ArchRegKind {
AREG_F1, // flag register
AREG_TM0, // timestamp register
AREG_TDR0, // TDR register
AREG_SP, // SP register
AREG_SP, // SP register
AREG_LAST
};
......
......@@ -79,6 +79,7 @@ G4_InstOptInfo InstOptInfo[] =
{InstOpt_EOT, "EOT"},
{InstOpt_AccWrCtrl, "AccWrEn"},
{InstOpt_Compacted, "Compacted"},
{InstOpt_NoCompact, "NoCompact" },
{InstOpt_NoSrcDepSet, "NoSrcDepSet"},
{InstOpt_NoPreempt, "NoPreempt"},
{InstOpt_END, "END"}
......@@ -510,7 +511,7 @@ G4_INST::G4_INST(const IR_Builder& irb,
G4_Operand* s0,
G4_Operand* s1,
unsigned int opt) :
op(o), dst(d), predicate(prd), mod(m), option(opt),
op(o), dst(d), predicate(prd), mod(m), option(opt),
local_id(0),
srcCISAoff(-1),
sat(s),
......@@ -553,7 +554,7 @@ G4_INST::G4_INST(const IR_Builder& irb,
G4_Operand* s1,
G4_Operand* s2,
unsigned int opt) :
op(o), dst(d), predicate(prd), mod(m), option(opt),
op(o), dst(d), predicate(prd), mod(m), option(opt),
local_id(0),
srcCISAoff(-1),
sat(s),
......@@ -1951,7 +1952,7 @@ bool G4_INST::canPropagateTo(G4_INST *useInst, Gen4_Operand_Number opndNum, MovT
// FIXME: to add specific checks for other instructions.
G4_opcode useInst_op = useInst->opcode();
if (useInst_op == G4_madm ||
(useInst->isMath() && (useInst->asMathInst()->getMathCtrl() == MATH_INVM || useInst->asMathInst()->getMathCtrl() == MATH_RSQRTM)))
{
......
......@@ -689,7 +689,7 @@ protected:
// during optimization, an inst may become redundant and be marked dead
unsigned short dead : 1;
unsigned short evenlySplitInst : 1;
unsigned char execSize;
unsigned char execSize;
BinInst *bin;
......@@ -701,7 +701,7 @@ protected:
public:
G4_INST(const IR_Builder& builder,
G4_INST(const IR_Builder& builder,
G4_Predicate* prd,
G4_opcode o,
G4_CondMod* m,
......@@ -822,7 +822,7 @@ public:
MUST_BE_TRUE(isIntrinsic(), ERROR_UNKNOWN);
return (G4_InstIntrinsic*) this;
}
G4_InstSend* asSendInst()
{
if (!isSend())
......@@ -864,19 +864,19 @@ public:
if (location != nullptr)
location->setLineNo(i);
}
int getLineNo() {
int getLineNo() {
if (location == nullptr)
return 0;
return location->getLineNo();
return location->getLineNo();
}
void setSrcFilename(char* filename) {
if (location != nullptr)
location->setSrcFilename(filename);
}
char* getSrcFilename() {
char* getSrcFilename() {
if (location == nullptr)
return nullptr;
return location->getSrcFilename();
return location->getSrcFilename();
}
void setDest(G4_DstRegRegion* opnd);
void setExecSize(unsigned char s);
......@@ -971,8 +971,10 @@ public:
return isAccDstInst() || implAccDst != NULL;
}
void setCompacted() { option = option | InstOpt_Compacted; }
bool isCompactedInst() { return (option & InstOpt_Compacted) ? true : false; }
void setCompacted() { option = option | InstOpt_Compacted; }
void setNoCompacted() { option = option | InstOpt_NoCompact; }
bool isCompactedInst() { return (option & InstOpt_Compacted) ? true : false; }
bool isNoCompactedInst() { return (option & InstOpt_NoCompact) ? true : false; }
void setLocalId(int32_t lid) { local_id = lid; }
int32_t getLocalId() const { return local_id; }
......@@ -1251,8 +1253,8 @@ class G4_InstCF : public G4_INST
// dst contains the ret IP and call mask.
// -- ret, fret: src0 contains the ret IP and call mask
// Note that for call/ret the retIP variable is not created till RA
G4_Label* jip; // GT JIP.
G4_Label* uip; // GT UIP.
G4_Label* jip; // GT JIP.
G4_Label* uip; // GT UIP.
// list of labels that this instruction could jump to. Only used for switch jmps
std::list<G4_Label*> indirectJmpTarget;
......@@ -1367,7 +1369,7 @@ public:
}
// for direct call, this is null till after the compilation units are stitched together
// for indirect call, this is src0
// for indirect call, this is src0
G4_Operand* getCalleeAddress() const
{
if (op == G4_pseudo_fcall)
......@@ -1413,9 +1415,9 @@ public:
};
class G4_InstSend : public G4_INST
{
{
G4_SendMsgDescriptor* msgDesc;
public:
// send (one source)
......@@ -1424,7 +1426,7 @@ public:
G4_InstSend(
const IR_Builder& builder,
G4_Predicate* prd,
G4_opcode o,
G4_opcode o,
unsigned char size,
G4_DstRegRegion* dst,
G4_SrcRegRegion* payload,
......@@ -1499,13 +1501,13 @@ public:
unsigned FC = MD->getFuncCtrl();
// Memory Fence
if (sfid == SFID::DP_DC && ((FC >> 14) & 0x1F) == DC_MEMORY_FENCE)
if (sfid == SFID::DP_DC && ((FC >> 14) & 0x1F) == DC_MEMORY_FENCE)
{
return true;
}
// Sampler cache flush
if (sfid == SFID::SAMPLER && ((FC >> 12) & 0x1F) == 0x1F)
if (sfid == SFID::SAMPLER && ((FC >> 12) & 0x1F) == 0x1F)
{
return true;
}
......@@ -1876,24 +1878,24 @@ class G4_Declare
uint16_t refInSend : 1;
unsigned int decl_id; // global decl id for this builder
uint32_t numElements;
unsigned int numFlagElements;
// byte offset of this declare from the base declare. For top-level declares this value is 0
int offsetFromBase;
// if set to nonzero, indicates the declare is only used by subroutine "scopeID".
// it is used to prevent a subroutin-local declare from escaping its subroutine when doing liveness
unsigned scopeID;
unsigned scopeID;
// For GRFs, store byte offset of allocated GRF
unsigned int GRFBaseOffset;
// fields that are only ever referenced by RA and spill code
// ToDo: they should be moved out of G4_Declare and stored as maps in RA/spill
G4_Declare* spillDCL; // if an addr/flag var is spilled, SpillDCL is the location (GRF) holding spilled value
G4_Declare* addrTakenSpillFillDcl; // dcl to use for address taken spill/fill temp
// this should only be called by builder
......@@ -2301,19 +2303,19 @@ public:
return reinterpret_cast<G4_AddrExp*>(this);
}
G4_DstRegRegion* asDstRegRegion()
{
G4_DstRegRegion* asDstRegRegion()
{
#ifdef _DEBUG
if (!isDstRegRegion())
{
return nullptr;
}
#endif
return reinterpret_cast<G4_DstRegRegion*>(this);
return reinterpret_cast<G4_DstRegRegion*>(this);
}
G4_SrcRegRegion* asSrcRegRegion()
{
G4_SrcRegRegion* asSrcRegRegion()
{
#ifdef _DEBUG
if (!isSrcRegRegion())
{
......@@ -3545,7 +3547,7 @@ class G4_CondMod final : public G4_Operand
{
top_dcl = getBase()->asRegVar()->getDeclare();
if (getBase()->asRegVar()->getPhyReg())
if (getBase()->asRegVar()->getPhyReg())
{
left_bound = off * 16;
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
......@@ -3572,11 +3574,11 @@ public:
MUST_BE_TRUE(getBase()->isAreg(), ERROR_INTERNAL_ARGUMENT);
MUST_BE_TRUE(getBase()->asRegVar()->getPhyReg(), "getRegOff is called for non-PhyReg");
if (getBase()->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F0)
if (getBase()->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F0)
{
return 0;
}
else
else
{
return 1;
}
......
......@@ -261,6 +261,10 @@ void VISAKernelImpl::expandIndirectCallWithRegTarget()
m_builder->createImm(32, add_inst->getSrc(0)->getType()),
InstOpt_WriteEnable);
// Set no compated to make sure the ip calculation is correct
add_inst->setNoCompacted();
add_inst2->setNoCompacted();
// then update fcall's src0 to add's dst
fcall->setSrc(m_builder->Create_Src_Opnd_From_Dcl(
add_inst->getDst()->getTopDcl(), m_builder->getRegionScalar()), 0);
......
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