Commit a4f261be authored by Buqi Cheng's avatar Buqi Cheng Committed by gbsbuild

Internal feature

Change-Id: Iee95e3a634d650801c29ad736da58a13ef1cbded
parent c5b7415d
......@@ -294,7 +294,7 @@ public:
{
if (nElems * nRows * G4_Type_Table[ty].byteSize >= G4_GRF_REG_NBYTES)
{
dcl->setSubRegAlign(Sixteen_Word);
dcl->setSubRegAlign(SUB_ALIGNMENT_GRFALIGN);
}
else
{
......@@ -821,7 +821,7 @@ public:
if (m_options->getOption(vISA_enablePreemption))
{
G4_Declare *R0CopyDcl = createTempVar(8, Type_UD, Either, Sixteen_Word);
G4_Declare *R0CopyDcl = createTempVar(8, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN);
builtinR0 = R0CopyDcl;
}
......
......@@ -1629,7 +1629,8 @@ bool IR_Builder::isOpndAligned( G4_Operand *opnd, unsigned short &offset, int al
// component wise and may need to consider checking
// the accumulated result.
if ((AliasOffset % align_byte) != 0 ||
(Dcl && Dcl->getSubRegAlign() != Sixteen_Word &&
(Dcl && Dcl->getSubRegAlign() != SUB_ALIGNMENT_GRFALIGN &&
Dcl->getSubRegAlign() != Sixteen_Word &&
Dcl->getSubRegAlign() != Eight_Word) ||
AE->getOffset() % align_byte != 0) {
isAligned = false;
......
......@@ -369,8 +369,10 @@ G4_SubReg_Align Get_G4_SubRegAlign_From_Size( uint16_t size )
// identifying.
case 16:
return Eight_Word;
default:
case 32:
return Sixteen_Word;
default:
return SUB_ALIGNMENT_GRFALIGN;
}
}
......
This diff is collapsed.
......@@ -1566,7 +1566,7 @@ void HWConformity::moveSrcToGRF( INST_LIST_ITER it, uint32_t srcNum, uint16_t nu
inst->setSrc( newSrc, srcNum );
}
G4_Declare* dcl = builder.createTempVar( dclSize, src->getType(), Either, Sixteen_Word );
G4_Declare* dcl = builder.createTempVar( dclSize, src->getType(), Either, SUB_ALIGNMENT_GRFALIGN );
G4_DstRegRegion *dstRegion = builder.createDstRegRegion(
Direct,
dcl->getRegVar(),
......@@ -1759,4 +1759,4 @@ void HWConformity::removeBadSrc( INST_LIST_ITER& iter, G4_BB *bb, bool crossGRF
}
}
}
}
\ No newline at end of file
}
......@@ -82,7 +82,7 @@ G4_DstRegRegion* CoalesceSpillFills::generateCoalescedFill(unsigned int scratchO
char* dclName = kernel.fg.builder->getNameString(kernel.fg.mem, 32,
"COAL_FILL_%d", kernel.Declares.size());
auto fillDcl = kernel.fg.builder->createDeclareNoLookup(dclName, G4_GRF,
8, (unsigned short)dclSize, Type_UD, DeclareType::CoalescedFill);
NUM_DWORDS_PER_GRF, (unsigned short)dclSize, Type_UD, DeclareType::CoalescedFill);
fillDcl->setAlign(alignment);
fillDcl->setDoNotSpill();
......@@ -167,7 +167,7 @@ G4_Declare* CoalesceSpillFills::createCoalescedSpillDcl(unsigned int payloadSize
dclName = kernel.fg.builder->getNameString(kernel.fg.mem, 32,
"COAL_SPILL_%d", kernel.Declares.size());
spillDcl = kernel.fg.builder->createDeclareNoLookup(dclName, G4_GRF,
8, (unsigned short)payloadSize, Type_UD, DeclareType::CoalescedSpill);
NUM_DWORDS_PER_GRF, (unsigned short)payloadSize, Type_UD, DeclareType::CoalescedSpill);
spillDcl->setDoNotSpill();
......@@ -1382,7 +1382,7 @@ void CoalesceSpillFills::fixSendsSrcOverlap()
char* dclName = kernel.fg.builder->getNameString(kernel.fg.mem, 32,
"COPY_%d", kernel.Declares.size());
G4_Declare* copyDcl = kernel.fg.builder->createDeclareNoLookup(dclName, G4_GRF,
8, src1->getTopDcl()->getNumRows(),
NUM_DWORDS_PER_GRF, src1->getTopDcl()->getNumRows(),
Type_UD);
unsigned int elems = copyDcl->getNumElems();
......
......@@ -3041,7 +3041,7 @@ int IR_Builder::translateVISAMediaLoadInst(
original_dst = dstOpnd;
new_dcl = createTempVar( GENX_GRF_REG_SIZ/G4_Type_Table[Type_UD].byteSize,
Type_UD, Either, Sixteen_Word );
Type_UD, Either, SUB_ALIGNMENT_GRFALIGN );
G4_DstRegRegion tmp_dst( Direct,
new_dcl->getRegVar(),
0,
......@@ -3094,7 +3094,7 @@ int IR_Builder::translateVISAMediaLoadInst(
{
G4_Declare *new_dcl2 = createTempVar(
GENX_GRF_REG_SIZ/G4_Type_Table[original_dst->getType()].byteSize,
original_dst->getType(), Either, Sixteen_Word );
original_dst->getType(), Either, SUB_ALIGNMENT_GRFALIGN );
new_dcl2->setAliasDeclare( new_dcl, 0 );
......@@ -3408,7 +3408,7 @@ int IR_Builder::translateVISAGatherInst(
// From SKL, SLM messages forbid message header. Recalculate offset by
// adding global offset and force headerLess.
G4_Declare *dcl = Create_MRF_Dcl(numElt, eltOffOpnd->getType());
dcl->setSubRegAlign(Sixteen_Word);
dcl->setSubRegAlign(SUB_ALIGNMENT_GRFALIGN);
G4_DstRegRegion *newEltOffOpnd = Create_Dst_Opnd_From_Dcl(dcl, 1);
createInst(NULL, G4_add, NULL, false, numElt, newEltOffOpnd, eltOffOpnd, gOffOpnd, instOpt);
eltOffOpnd = Create_Src_Opnd_From_Dcl(dcl, numElt == 1 ? getRegionScalar() : getRegionStride1());
......@@ -3424,7 +3424,7 @@ int IR_Builder::translateVISAGatherInst(
G4_Declare *header = 0;
G4_Declare *offset = Create_MRF_Dcl(numElt, Type_UD);
offset->setSubRegAlign(Sixteen_Word);
offset->setSubRegAlign(SUB_ALIGNMENT_GRFALIGN);
if (useSplitSend)
{
......@@ -3885,7 +3885,7 @@ int IR_Builder::translateVISAGather4Inst(
// shl (esize) offset<1>:ud elt_off<8;8,1>:ud 2:uw
G4_DstRegRegion* dst1_opnd = createDstRegRegion(Direct, offset->getRegVar(), 0, 0, 1, offset->getElemType());
G4_Declare *tmp_dcl = createTempVar( numElt, Type_UD, Either, Sixteen_Word );
G4_Declare *tmp_dcl = createTempVar( numElt, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN );
G4_DstRegRegion dst3( Direct, tmp_dcl->getRegVar(), 0, 0, 1, tmp_dcl->getElemType() );
G4_DstRegRegion* dst3_opnd = createDstRegRegion( dst3 );
......@@ -4106,7 +4106,7 @@ int IR_Builder::translateVISAScatter4Inst(
G4_DstRegRegion* dst1_opnd = createDstRegRegion(Direct, offset->getRegVar(), 0, 0, 1, offset->getElemType());
G4_Declare *tmp_dcl = createTempVar( numElt, Type_UD, Either, Sixteen_Word );
G4_Declare *tmp_dcl = createTempVar( numElt, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN );
G4_DstRegRegion dst3( Direct, tmp_dcl->getRegVar(), 0, 0, 1, tmp_dcl->getElemType() );
G4_DstRegRegion* dst3_opnd = createDstRegRegion( dst3 );
......@@ -6124,7 +6124,7 @@ int IR_Builder::translateVISALogicInst(ISA_Opcode opcode, G4_Predicate *predOpnd
// split into
// bfi1 tmp src0 src1
// bfi2 dst tmp src2 src3
G4_Declare* tmpDcl = createTempVar( exsize, g4Srcs[0]->getType(), Either, Sixteen_Word);
G4_Declare* tmpDcl = createTempVar( exsize, g4Srcs[0]->getType(), Either, SUB_ALIGNMENT_GRFALIGN);
G4_DstRegRegion* tmpDst = Create_Dst_Opnd_From_Dcl( tmpDcl, 1);
createInst(
predOpnd,
......@@ -9189,7 +9189,7 @@ static int splitSampleInst(VISASampler3DSubOpCode actualop,
uint8_t execSize = 8;
uint16_t numElts = numRows * GENX_GRF_REG_SIZ/G4_Type_Table[Type_F].byteSize;
G4_Declare* payloadF = builder->Create_MRF_Dcl( numElts, Type_F );
G4_Declare* payloadUD = builder->createTempVar( numElts, Type_UD, Either, Sixteen_Word );
G4_Declare* payloadUD = builder->createTempVar( numElts, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN );
payloadUD->setAliasDeclare( payloadF, 0 );
G4_SrcRegRegion* srcToUse = builder->createSrcRegRegion(Mod_src_undef, Direct, payloadUD->getRegVar(), 0, 0, builder->getRegionStride1(), Type_UD);
......@@ -9319,15 +9319,15 @@ static int splitSampleInst(VISASampler3DSubOpCode actualop,
if(pixelNullMaskEnable)
{
unsigned int numElts = tempDstDcl->getNumElems() * tempDstDcl->getNumRows();
tempDstUD = builder->createTempVar(numElts, Type_UD, Either, Sixteen_Word);
tempDstUD = builder->createTempVar(numElts, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN);
tempDstUD->setAliasDeclare(tempDstDcl, 0);
numElts = tempDstDcl2->getNumElems() * tempDstDcl2->getNumRows();
tempDst2UD = builder->createTempVar(numElts, Type_UD, Either, Sixteen_Word);
tempDst2UD = builder->createTempVar(numElts, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN);
tempDst2UD->setAliasDeclare(tempDstDcl2, 0);
numElts = originalDstDcl->getNumElems() * originalDstDcl->getNumRows();
origDstUD = builder->createTempVar(numElts, Type_UD, Either, Sixteen_Word);
origDstUD = builder->createTempVar(numElts, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN);
origDstUD->setAliasDeclare(originalDstDcl, 0);
}
......@@ -9348,7 +9348,7 @@ static int splitSampleInst(VISASampler3DSubOpCode actualop,
/**************** SECOND HALF OF THE SEND *********************/
// re-create payload declare so the two sends may be issued independently
G4_Declare* payloadF = builder->Create_MRF_Dcl(numElts, Type_F);
G4_Declare* payloadUD = builder->createTempVar(numElts, Type_UD, Either, Sixteen_Word);
G4_Declare* payloadUD = builder->createTempVar(numElts, Type_UD, Either, SUB_ALIGNMENT_GRFALIGN);
payloadUD->setAliasDeclare(payloadF, 0);
// even though we only use lower half of the GRF, we have to allocate full GRF
......
......@@ -182,8 +182,8 @@ static void setDeclAlignment(G4_Declare* dcl, VISA_Align align)
case ALIGN_DWORD: dcl->setAlign(Either); dcl->setSubRegAlign(Even_Word); break;//dword aligned;
case ALIGN_QWORD: dcl->setAlign(Either); dcl->setSubRegAlign(Four_Word); break;//8 byte aligned;
case ALIGN_OWORD: dcl->setAlign(Either); dcl->setSubRegAlign(Eight_Word); break;//oword aligned;
case ALIGN_GRF: dcl->setAlign(Either); dcl->setSubRegAlign(Sixteen_Word); break;//grf aligned;
case ALIGN_2_GRF: dcl->setAlign(Even); dcl->setSubRegAlign(Sixteen_Word); break; //2 grf aligned;
case ALIGN_GRF: dcl->setAlign(Either); dcl->setSubRegAlign(SUB_ALIGNMENT_GRFALIGN); break;//grf aligned;
case ALIGN_2_GRF: dcl->setAlign(Even); dcl->setSubRegAlign(SUB_ALIGNMENT_GRFALIGN); break; //2 grf aligned;
default: assert(false && "Incorrect vISA alignment"); break;
}
}
......@@ -815,7 +815,7 @@ int VISAKernelImpl::CreateVISAGenVar(VISA_GenVar *& decl, const char *varName, i
}
// force subalign to be GRF if total size is larger than or equal to GRF
if (info->dcl->getSubRegAlign() != Sixteen_Word)
if (info->dcl->getSubRegAlign() != SUB_ALIGNMENT_GRFALIGN)
{
setDeclAlignment(info->dcl, varAlign);
}
......
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