Commit b50b6ee3 authored by Rishipal Singh Bhatia's avatar Rishipal Singh Bhatia Committed by gbsbuild

With this chnage I am adding the simdBlockreads instricsic to be

promoted from stateless to bindless.

The convolution shader uses this as subgroup_block_read and IGC keeps
that as stateless.

Change-Id: I5f58747ef0f59526dac9049cdcb0fa80ea59eaf2
parent 3190142d
...@@ -6997,6 +6997,9 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst) ...@@ -6997,6 +6997,9 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst)
case GenISAIntrinsic::GenISA_simdBlockRead: case GenISAIntrinsic::GenISA_simdBlockRead:
emitSimdBlockRead(inst); emitSimdBlockRead(inst);
break; break;
case GenISAIntrinsic::GenISA_simdBlockReadBindless:
emitSimdBlockRead(inst, inst->getOperand(1));
break;
case GenISAIntrinsic::GenISA_simdBlockWrite: case GenISAIntrinsic::GenISA_simdBlockWrite:
emitSimdBlockWrite(inst); emitSimdBlockWrite(inst);
break; break;
......
...@@ -182,6 +182,7 @@ DECLARE_OPCODE(GenISA_simdLaneId, GenISAIntrinsic, llvm_s ...@@ -182,6 +182,7 @@ DECLARE_OPCODE(GenISA_simdLaneId, GenISAIntrinsic, llvm_s
DECLARE_OPCODE(GenISA_simdSize, GenISAIntrinsic, llvm_simdSize, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdSize, GenISAIntrinsic, llvm_simdSize, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdShuffleDown, GenISAIntrinsic, llvm_simdShuffleDown, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdShuffleDown, GenISAIntrinsic, llvm_simdShuffleDown, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdBlockRead, GenISAIntrinsic, llvm_simdBlockRead, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdBlockRead, GenISAIntrinsic, llvm_simdBlockRead, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdBlockReadBindless, GenISAIntrinsic, llvm_simdBlockReadBindless, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdBlockWrite, GenISAIntrinsic, llvm_simdBlockWrite, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdBlockWrite, GenISAIntrinsic, llvm_simdBlockWrite, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdMediaBlockRead, GenISAIntrinsic, llvm_simdMediaBlockRead, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdMediaBlockRead, GenISAIntrinsic, llvm_simdMediaBlockRead, false, false, false, false, false, false, false )
DECLARE_OPCODE(GenISA_simdMediaBlockWrite, GenISAIntrinsic, llvm_simdMediaBlockWrite, false, false, false, false, false, false, false ) DECLARE_OPCODE(GenISA_simdMediaBlockWrite, GenISAIntrinsic, llvm_simdMediaBlockWrite, false, false, false, false, false, false, false )
......
...@@ -117,6 +117,7 @@ Value* GetBufferOperand(Instruction* inst) ...@@ -117,6 +117,7 @@ Value* GetBufferOperand(Instruction* inst)
case GenISAIntrinsic::GenISA_floatatomicraw: case GenISAIntrinsic::GenISA_floatatomicraw:
case GenISAIntrinsic::GenISA_icmpxchgatomicraw: case GenISAIntrinsic::GenISA_icmpxchgatomicraw:
case GenISAIntrinsic::GenISA_fcmpxchgatomicraw: case GenISAIntrinsic::GenISA_fcmpxchgatomicraw:
case GenISAIntrinsic::GenISA_simdBlockRead:
pBuffer = intr->getOperand(0); pBuffer = intr->getOperand(0);
break; break;
case GenISAIntrinsic::GenISA_intatomicrawA64: case GenISAIntrinsic::GenISA_intatomicrawA64:
...@@ -750,11 +751,17 @@ void PromoteResourceToDirectAS::GetAccessInstToSrcPointerMap(Instruction* inst, ...@@ -750,11 +751,17 @@ void PromoteResourceToDirectAS::GetAccessInstToSrcPointerMap(Instruction* inst,
return; return;
} }
//We only support loadInst, StoreInst and GenISA_simdBlockRead intrinsic
if (!isa<LoadInst>(inst) && !isa<StoreInst>(inst)) if (!isa<LoadInst>(inst) && !isa<StoreInst>(inst))
{ {
// Do we need to support other instructions besides load/store? if (GenIntrinsicInst* GInst = dyn_cast<GenIntrinsicInst>(inst))
return; {
} if (GInst->getIntrinsicID() != GenISAIntrinsic::GenISA_simdBlockRead)
return;
}
else
return;
}
Value* srcPtr = IGC::TracePointerSource(resourcePtr); Value* srcPtr = IGC::TracePointerSource(resourcePtr);
...@@ -820,6 +827,18 @@ void PromoteResourceToDirectAS::PromoteStatelessToBindlessBuffers(Function& F) ...@@ -820,6 +827,18 @@ void PromoteResourceToDirectAS::PromoteStatelessToBindlessBuffers(Function& F)
IGC::CreateStoreRawIntrinsic(store, cast<Instruction>(basePointer), bufferOffset); IGC::CreateStoreRawIntrinsic(store, cast<Instruction>(basePointer), bufferOffset);
store->eraseFromParent(); store->eraseFromParent();
} }
else if (GenIntrinsicInst* pIntr = dyn_cast<GenIntrinsicInst>(accessInst))
{
if (pIntr->getIntrinsicID() == GenISAIntrinsic::GenISA_simdBlockRead)
{
Function* newBlockReadFunc = GenISAIntrinsic::getDeclaration(F.getParent(),
GenISAIntrinsic::GenISA_simdBlockReadBindless,
{ accessInst->getType(),basePointer->getType(),Type::getInt32Ty(accessInst->getContext()) });
Instruction* newBlockRead = CallInst::Create(newBlockReadFunc, { basePointer, bufferOffset }, "", accessInst);
accessInst->replaceAllUsesWith(newBlockRead);
accessInst->eraseFromParent();
}
}
} }
} }
......
...@@ -193,6 +193,7 @@ Imported_Intrinsics = \ ...@@ -193,6 +193,7 @@ Imported_Intrinsics = \
"GenISA_simdSize": ["int",[],"NoMem"], "GenISA_simdSize": ["int",[],"NoMem"],
"GenISA_simdShuffleDown": ["anyint",[0,0,"int"],"Convergent,NoMem"], "GenISA_simdShuffleDown": ["anyint",[0,0,"int"],"Convergent,NoMem"],
"GenISA_simdBlockRead": ["anyvector",["anyptr"],"ReadMem"], "GenISA_simdBlockRead": ["anyvector",["anyptr"],"ReadMem"],
"GenISA_simdBlockReadBindless": ["anyvector",["anyptr", "int"],"ReadMem"],
"GenISA_simdBlockWrite": ["void",["anyptr","anyvector"],"None"], "GenISA_simdBlockWrite": ["void",["anyptr","anyvector"],"None"],
"GenISA_MediaBlockRead": ["anyint",["int","int","int","int","int","int"],"None"], "GenISA_MediaBlockRead": ["anyint",["int","int","int","int","int","int"],"None"],
"GenISA_MediaBlockWrite": ["void",["int","int","int","int","int","int","anyint"],"None"], "GenISA_MediaBlockWrite": ["void",["int","int","int","int","int","int","anyint"],"None"],
......
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