Commit dc36b0bd authored by paigeale's avatar paigeale Committed by Paige, Alexander

Open Sourcing Gen 11 content for IGC / Clean up fixes in files

Change-Id: Ic329c0e27af25725b41544223f7e5379eb799c3a
parent 414c4585
......@@ -69,7 +69,8 @@ typedef enum
GEN_ISA_TYPE_GEN7p5 = 3,
GEN_ISA_TYPE_GEN8 = 4,
GEN_ISA_TYPE_GEN9 = 5,
GEN_ISA_TYPE_GEN10 = 6
GEN_ISA_TYPE_GEN10 = 6,
GEN_ISA_TYPE_GEN11 = 7
} GEN_ISA_TYPE;
typedef enum
......
......@@ -589,6 +589,10 @@ void __builtin_IB_media_block_write_ulong2(int image, int2 offset, int width, in
void __builtin_IB_media_block_write_ulong4(int image, int2 offset, int width, int height, ulong4 pixels);
void __builtin_IB_media_block_write_ulong8(int image, int2 offset, int width, int height, ulong8 pixels);
int __builtin_IB_dp4a_ss(int c, int a, int b) __attribute__((const));
int __builtin_IB_dp4a_uu(int c, int a, int b) __attribute__((const));
int __builtin_IB_dp4a_su(int c, int a, int b) __attribute__((const));
int __builtin_IB_dp4a_us(int c, int a, int b) __attribute__((const));
short __builtin_IB_sub_group_reduce_OpGroupIAdd_i16(short x) __attribute__((const));
short __builtin_IB_sub_group_reduce_OpGroupSMax_i16(short x) __attribute__((const));
......
......@@ -2691,6 +2691,19 @@ TARGET_PLATFORM GetVISAPlatform(const CPlatform* platform)
{
return GENX_SKL;
}
case IGFX_GEN10_CORE:
return GENX_CNL;
case IGFX_GEN11_CORE:
if (platform->getPlatformInfo().eProductFamily == IGFX_ICELAKE_LP ||
platform->getPlatformInfo().eProductFamily == IGFX_LAKEFIELD ||
platform->getPlatformInfo().eProductFamily == IGFX_JASPERLAKE)
{
return GENX_ICLLP;
}
else
{
return GENX_ICL;
}
default:
assert(0 && "unsupported platform");
break;
......@@ -2959,6 +2972,8 @@ void CEncoder::GenericAlu(e_opcode opcode, CVariable* dst, CVariable* src0, CVar
case ISA_OR:
case ISA_SHL:
case ISA_SHR:
case ISA_ROL:
case ISA_ROR:
case ISA_XOR:
LogicOp(visaOpcode, dst, src0, src1, src2);
break;
......@@ -5148,8 +5163,8 @@ void CEncoder::SetVISAWaTable(WA_TABLE const& waTable)
}
if (m_program->m_Platform->supportFtrWddm2Svm() ||
m_program->m_Platform->GetPlatformFamily() == IGFX_GEN10_CORE
)
m_program->m_Platform->GetPlatformFamily() == IGFX_GEN10_CORE ||
m_program->m_Platform->GetPlatformFamily() == IGFX_GEN11_CORE)
{
// no send src/dst overlap when page fault is enabled
m_WaTable.WaDisableSendSrcDstOverlap = true;
......
......@@ -282,6 +282,7 @@ public:
inline void IEEEDivide(CVariable* dst, CVariable* src0, CVariable* src1);
void AddPair(CVariable *Lo, CVariable *Hi, CVariable *L0, CVariable *H0, CVariable *L1, CVariable *H1);
void SubPair(CVariable *Lo, CVariable *Hi, CVariable *L0, CVariable *H0, CVariable *L1, CVariable *H1);
inline void dp4a(CVariable* dst, CVariable* src0, CVariable* src1, CVariable* src2);
// VME
void SendVmeIme(
CVariable* bindingTableIndex,
......@@ -784,6 +785,9 @@ inline void CEncoder::IEEEDivide(CVariable* dst, CVariable* src0, CVariable* src
Arithmetic(ISA_DIVM, dst, src0, src1);
}
inline void CEncoder::dp4a(CVariable* dst, CVariable* src0, CVariable* src1, CVariable* src2) {
Arithmetic(ISA_DP4A, dst, src0, src1, src2);
}
inline void CEncoder::SetNoMask()
{
......
......@@ -77,6 +77,7 @@ set(IGC_BUILD__SRC__CISACodeGen_Common
"${CMAKE_CURRENT_SOURCE_DIR}/VertexShaderLowering.cpp"
"${CMAKE_CURRENT_SOURCE_DIR}/WIAnalysis.cpp"
"${CMAKE_CURRENT_SOURCE_DIR}/SLMConstProp.cpp"
"${CMAKE_CURRENT_SOURCE_DIR}/POSH_RemoveNonPositionOutput.cpp"
)
......@@ -161,6 +162,7 @@ set(IGC_BUILD__HDR__CISACodeGen_Common
"${CMAKE_CURRENT_SOURCE_DIR}/VertexShaderLowering.hpp"
"${CMAKE_CURRENT_SOURCE_DIR}/WIAnalysis.hpp"
"${CMAKE_CURRENT_SOURCE_DIR}/SLMConstProp.hpp"
"${CMAKE_CURRENT_SOURCE_DIR}/POSH_RemoveNonPositionOutput.h"
)
......
......@@ -7238,6 +7238,12 @@ void EmitPass::EmitGenIntrinsicMessage(llvm::GenIntrinsicInst* inst)
case GenISAIntrinsic::GenISA_GetPixelMask:
emitGetPixelMask(inst);
break;
case GenISAIntrinsic::GenISA_dp4a_ss:
case GenISAIntrinsic::GenISA_dp4a_uu:
case GenISAIntrinsic::GenISA_dp4a_su:
case GenISAIntrinsic::GenISA_dp4a_us:
emitDP4A(inst);
break;
case GenISAIntrinsic::GenISA_evaluateSampler:
// nothing to do
break;
......@@ -13910,4 +13916,29 @@ void EmitPass::emitWaveAll(llvm::GenIntrinsicInst* inst)
emitReductionAll(opCode, identity, type, false, src, dst);
}
void EmitPass::emitDP4A(GenIntrinsicInst* GII) {
GenISAIntrinsic::ID GIID = GII->getIntrinsicID();
CVariable* dst = m_destination;
CVariable* src0 = GetSymbol(GII->getOperand(0));
CVariable* src1 = GetSymbol(GII->getOperand(1));
CVariable* src2 = GetSymbol(GII->getOperand(2));
// Set correct signedness of src1.
if (GIID == GenISAIntrinsic::GenISA_dp4a_ss ||
GIID == GenISAIntrinsic::GenISA_dp4a_su)
src1 = m_currShader->BitCast(src1, ISA_TYPE_D);
if (GIID == GenISAIntrinsic::GenISA_dp4a_uu ||
GIID == GenISAIntrinsic::GenISA_dp4a_us)
src1 = m_currShader->BitCast(src1, ISA_TYPE_UD);
// Set correct signedness of src2.
if (GIID == GenISAIntrinsic::GenISA_dp4a_ss ||
GIID == GenISAIntrinsic::GenISA_dp4a_us)
src2 = m_currShader->BitCast(src2, ISA_TYPE_D);
if (GIID == GenISAIntrinsic::GenISA_dp4a_uu ||
GIID == GenISAIntrinsic::GenISA_dp4a_su)
src2 = m_currShader->BitCast(src2, ISA_TYPE_UD);
// Emit dp4a.
m_encoder->dp4a(dst, src0, src1, src2);
m_encoder->Push();
}
......@@ -366,6 +366,7 @@ public:
void emitRsq(llvm::Instruction *inst);
void emitLLVMbswap(llvm::IntrinsicInst* inst);
void emitDP4A(llvm::GenIntrinsicInst *GII);
// Debug Built-Ins
void emitStateRegID(uint64_t and_imm, uint64_t shr_imm);
......
/*===================== begin_copyright_notice ==================================
Copyright (c) 2017 Intel Corporation
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
======================= end_copyright_notice ==================================*/
#include "Compiler/IGCPassSupport.h"
#include "common/LLVMWarningsPush.hpp"
#include "llvm/IR/InstIterator.h"
#include "common/LLVMWarningsPop.hpp"
#include "GenISAIntrinsics/GenIntrinsicInst.h"
#include "Compiler/CodeGenPublicEnums.h"
#include "Compiler/CISACodeGen/helper.h"
#include <llvm/IR/PassManager.h>
using namespace IGC;
using namespace llvm;
class RemoveNonPositionOutput : public llvm::FunctionPass
{
public:
static char ID;
RemoveNonPositionOutput();
~RemoveNonPositionOutput() {}
virtual void getAnalysisUsage(llvm::AnalysisUsage &AU) const override
{
AU.setPreservesCFG();
}
virtual bool runOnFunction(llvm::Function &F) override;
virtual llvm::StringRef getPassName() const override
{
return "remove non-position output in vertex shader";
}
};
llvm::FunctionPass* createRemoveNonPositionOutputPass()
{
return new RemoveNonPositionOutput();
}
// Register pass to igc-opt
#define PASS_FLAG_POSH "igc-remove-nonposition-output"
#define PASS_DESCRIPTION_POSH "Custom Pass for Position-Only Shader"
#define PASS_CFG_ONLY_POSH false
#define PASS_ANALYSIS_POSH false
IGC_INITIALIZE_PASS_BEGIN(RemoveNonPositionOutput, PASS_FLAG_POSH, PASS_DESCRIPTION_POSH, PASS_CFG_ONLY_POSH, PASS_ANALYSIS_POSH)
IGC_INITIALIZE_PASS_END(RemoveNonPositionOutput, PASS_FLAG_POSH, PASS_DESCRIPTION_POSH, PASS_CFG_ONLY_POSH, PASS_ANALYSIS_POSH)
char RemoveNonPositionOutput::ID = 0;
RemoveNonPositionOutput::RemoveNonPositionOutput() : FunctionPass(ID)
{
initializeRemoveNonPositionOutputPass(*PassRegistry::getPassRegistry());
}
bool RemoveNonPositionOutput::runOnFunction(Function &F)
{
// Initialize the worklist to all of the instructions ready to process...
SmallVector<Instruction*, 10> instructionToRemove;
for (inst_iterator II = inst_begin(F), E = inst_end(F); II != E; ++II)
{
if (GenIntrinsicInst *inst = dyn_cast<GenIntrinsicInst>(&*II))
{
if (inst->getIntrinsicID() == GenISAIntrinsic::GenISA_OUTPUT)
{
const ShaderOutputType usage = static_cast<ShaderOutputType>(
llvm::cast<llvm::ConstantInt>(inst->getOperand(4))->getZExtValue());
if (usage != SHADER_OUTPUT_TYPE_POSITION &&
usage != SHADER_OUTPUT_TYPE_POINTWIDTH &&
usage != SHADER_OUTPUT_TYPE_VIEWPORT_ARRAY_INDEX &&
usage != SHADER_OUTPUT_TYPE_CLIPDISTANCE_LO &&
usage != SHADER_OUTPUT_TYPE_CLIPDISTANCE_HI)
{
instructionToRemove.push_back(inst);
}
}
}
}
bool changed = false;
uint num = instructionToRemove.size();
for (uint i = 0; i < num; ++i)
{
instructionToRemove[i]->eraseFromParent();
changed = true;
}
return changed;
}
\ No newline at end of file
/*===================== begin_copyright_notice ==================================
Copyright (c) 2017 Intel Corporation
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be included
in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
======================= end_copyright_notice ==================================*/
#pragma once
llvm::FunctionPass* createRemoveNonPositionOutputPass();
\ No newline at end of file
......@@ -2786,6 +2786,230 @@ bool CodeGenPatternMatch::MatchBoolOp(llvm::BinaryOperator& I)
return found;
}
//
// Assume that V is of type T (integer) with N bits;
// and amt is of integer type too.
//
// rol (V, amt) = (V << amt) | ((unsigned(V) >> (N - amt))
// The function first finds the following generic pattern, note that
// [insts] denotes that "insts" are optional.
// [amt = and amt, N-1]
// high = shl V0, amt
// [amt0 = sub 0, amt || amt0 = sub N, amt]
// ; if amt is constant && amt + amt0 == N, this is unneeded
// [amt0 = and amt0, N-1]
// low = lshr V1, amt0
// R = or high, low
//
// case 0: [ likely, V is i32 or i64]
// V0 == V1 (V == V0 == V1)
//
// case 1: [ likely V is i16 or i8]
// V0 = sext V || zext V
// V1 = zext V
// Res = trunc R
//
// Res's type == V's type
//
// ror can be handled similarly. Note that
// ror (x, amt) = ((unsigned)x >> amt) | ( x << (N - amt))
// = rol (x, N - amt);
//
bool CodeGenPatternMatch::MatchRotate(llvm::Instruction& I)
{
using namespace llvm::PatternMatch;
struct RotatePattern : public Pattern
{
SSource sources[2];
e_opcode rotateOPCode;
llvm::Instruction* instruction;
virtual void Emit(EmitPass* pass, const DstModifier& modifier)
{
pass->Binary(rotateOPCode, sources, modifier);
}
};
if (!m_Platform.supportRotateInstruction())
{
return false;
}
// Sanity check:
// make sure that rotate is supported and "I" is a scalar "or" instruction
assert(!I.getType()->isVectorTy() && "Vector type not expected here");
uint64_t typeWidth = I.getType()->getScalarSizeInBits();
Instruction *OrInst = nullptr;
if (I.getOpcode() == Instruction::Trunc)
{
if (BinaryOperator *tmp = dyn_cast<BinaryOperator>(I.getOperand(0)))
{
if (tmp->getOpcode() != Instruction::Or)
{
return false;
}
OrInst = tmp;
}
else
{
return false;
}
}
else if (I.getOpcode() == Instruction::Or)
{
OrInst = cast<BinaryOperator>(&I);
}
else
{
assert(false && "Should be invoked with Or/Trunc instruction");
}
// Do rotate only if
// 1) type is W/DW (HW only supports W/DW); and
// 2) both operands are instructions.
Instruction *LHS = dyn_cast<Instruction>(OrInst->getOperand(0));
Instruction *RHS = dyn_cast<Instruction>(OrInst->getOperand(1));
if (!LHS || !RHS ||
(typeWidth != 16 && typeWidth != 32))
{
return false;
}
// Make adjustment so that LHS is shl.
if (LHS->getOpcode() == Instruction::LShr)
{
Instruction *t = LHS;
LHS = RHS;
RHS = t;
}
if (LHS->getOpcode() != Instruction::Shl ||
RHS->getOpcode() != Instruction::LShr)
{
return false;
}
// first: find V
Value *V0 = LHS->getOperand(0);
Value *V1 = RHS->getOperand(0);
Value *V = nullptr;
if (I.getOpcode() == Instruction::Or)
{
if (V0 == V1)
{
V = V0;
}
}
else
{
Value *X0, *X1;
if ((match(V0, m_ZExt(m_Value(X0))) || match(V0, m_SExt(m_Value(X0)))) &&
match(V1, m_ZExt(m_Value(X1))))
{
if (X0 == X1 && X0->getType()->getScalarSizeInBits() == typeWidth)
{
V = X0;
}
}
}
if (!V)
{
return false;
}
// Second: find amt
uint64_t typeMask = typeWidth - 1;
Value *LAmt = LHS->getOperand(1);
Value *RAmt = RHS->getOperand(1);
ConstantInt *C_LAmt = dyn_cast<ConstantInt>(LAmt);
ConstantInt *C_RAmt = dyn_cast<ConstantInt>(RAmt);
Value *X0, *X1;
Value *Amt = nullptr;
bool isROL = true;
if (C_LAmt || C_RAmt)
{
// If only one of shift-amounts is constant, it cannot be rotate.
if (C_LAmt && C_RAmt)
{
// For shift amount that is beyond the typewidth, the result is
// undefined. Here, we just use the LSB.
uint64_t c0 = C_LAmt->getZExtValue() & typeMask;
uint64_t c1 = C_RAmt->getZExtValue() & typeMask;
if ((c0 + c1) == typeWidth)
{
Amt = LAmt;
isROL = true;
}
}
}
else
{
if (match(RAmt, m_And(m_Sub(m_Zero(), m_Value(X1)), m_SpecificInt(typeMask))) ||
match(RAmt, m_And(m_Sub(m_SpecificInt(typeWidth), m_Value(X1)), m_SpecificInt(typeMask))) ||
match(RAmt, m_Sub(m_Zero(), m_Value(X1))) ||
match(RAmt, m_Sub(m_SpecificInt(typeWidth), m_Value(X1))))
{
if (LAmt == X1 ||
(match(LAmt, m_And(m_Value(X0), m_SpecificInt(typeMask))) && (X1 == X0)))
{
Amt = X1;
isROL = true;
}
}
if (!Amt &&
(match(LAmt, m_And(m_Sub(m_Zero(), m_Value(X1)), m_SpecificInt(typeMask))) ||
match(LAmt, m_And(m_Sub(m_SpecificInt(typeWidth), m_Value(X1)), m_SpecificInt(typeMask))) ||
match(LAmt, m_Sub(m_Zero(), m_Value(X1))) ||
match(LAmt, m_Sub(m_SpecificInt(typeWidth), m_Value(X1)))))
{
if (RAmt == X1 ||
(match(RAmt, m_And(m_Value(X0), m_SpecificInt(typeMask))) && (X1 == X0)))
{
Amt = X1;
isROL = false;
}
}
if (Amt)
{
Value *X0, *X1, *X2;
// 1) simple case: amt = 32 - X0; use amt1 as shift amount.
bool isReverse = match(Amt, m_Sub(m_SpecificInt(typeWidth), m_Value(X0)));
// 2) t = 16 - X0 | t = 0 - X0 ; for example, t is i16/i8, etc
// t1 = t & 15
// amt = zext t1, i32
isReverse = isReverse ||
(match(Amt, m_ZExt(m_Value(X1))) &&
match(X1, m_And(m_Value(X2), m_SpecificInt(typeMask))) &&
(match(X2, m_Sub(m_SpecificInt(typeWidth), m_Value(X0))) ||
match(X2, m_Sub(m_Zero(), m_Value(X0)))));
if (isReverse)
{
Amt = X0;
isROL = !isROL;
}
}
}
if (!Amt)
{
return false;
}
// Found the pattern.
RotatePattern *pattern = new (m_allocator) RotatePattern();
pattern->instruction = &I;
pattern->sources[0] = GetSource(V, true, false);
pattern->sources[1] = GetSource(Amt, true, false);
pattern->rotateOPCode = isROL ? EOPCODE_ROL : EOPCODE_ROR;
AddPattern(pattern);
return true;
}
bool CodeGenPatternMatch::MatchLogicAlu(llvm::BinaryOperator& I)
{
......
......@@ -203,6 +203,7 @@ public:
bool MatchPow(llvm::IntrinsicInst& I);
bool MatchCondModifier(llvm::CmpInst& I);
bool MatchBoolOp(llvm::BinaryOperator& I);
bool MatchRotate(llvm::Instruction& I);
bool MatchLogicAlu(llvm::BinaryOperator& I);
bool MatchRsqrt(llvm::BinaryOperator& I);
bool MatchLoadStorePointer(llvm::Instruction& I, llvm::Value& ptrVal);
......
......@@ -175,6 +175,55 @@ public:
return m_platformInfo.eRenderCoreFamily >= IGFX_GEN10_CORE;
}
bool hasPSDBottleneck() const { return m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE; }
bool supportsHardwareResourceStreamer() const
{
return m_platformInfo.eRenderCoreFamily < IGFX_GEN11_CORE;
}
bool AOComputeShadersSIMD32Mode() const
{
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE);
}
unsigned int getHullShaderThreadInstanceIdBitFieldPosition() const
{
// HS thread receives instance ID in R0.2 bits 22:16 for Gen10+ and bits 23:17 for older Gens
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE) ? 16 : 17;
}
bool supportsBinaryAtomicCounterMessage() const
{
return m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE;
}
bool supportSLMBlockMessage() const
{
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE);
}
bool supportRotateInstruction() const { return m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE; }
bool supportLRPInstruction() const { return m_platformInfo.eRenderCoreFamily < IGFX_GEN11_CORE; }
bool support16bitMSAAPayload() const { return m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE; }
bool supportTwoStackTSG() const
{
//Will need check for specific skus where TwoStackTSG is enabled
//Not all skus have it enabled
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE);
}
bool enableBlendToDiscardAndFill() const
{
return (m_platformInfo.eRenderCoreFamily < IGFX_GEN11_CORE);
}
bool HSUsesHWBarriers() const
{
// HS HW barriers work correctly since ICL platform.
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE);
}
bool applyTEFactorsPadding() const
{
return m_platformInfo.eRenderCoreFamily >= IGFX_GEN11_CORE;
}
bool enableVertexReorderingPhase2() const
{
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN10_CORE);
}
bool supportsSIMD16TypedRW() const
{
return false;
......@@ -190,30 +239,19 @@ public:
return IGC_IS_FLAG_DISABLED(ForceSWCoalescingOfAtomicCounter);
}
bool hasPSDBottleneck() const { return false; }
bool supportsHardwareResourceStreamer() const
{
return true;
}
bool AOComputeShadersSIMD32Mode() const
{
return false;
}
unsigned int getHullShaderThreadInstanceIdBitFieldPosition() const
{
// HS thread receives instance ID in R0.2 bits 22:16 for Gen10+
return 17;
}
//all the platforms which do not support 64 bit operations (int64 and double)
bool hasNo64BitInst() const {
return false;
return m_platformInfo.eProductFamily == IGFX_GLENVIEW ||
m_platformInfo.eProductFamily == IGFX_ICELAKE_LP ||
m_platformInfo.eProductFamily == IGFX_LAKEFIELD ||
m_platformInfo.eProductFamily == IGFX_JASPERLAKE;
}
//all the platforms which have correctly rounded macros (INVM, RSQRTM, MADM)
bool hasCorrectlyRoundedMacros() const {
return true;
return m_platformInfo.eProductFamily != IGFX_GLENVIEW &&
m_platformInfo.eProductFamily != IGFX_ICELAKE_LP &&
m_platformInfo.eProductFamily != IGFX_LAKEFIELD;
}
//all the platforms which do not support 64 bit operations and
......@@ -222,17 +260,23 @@ public:
//Emulating it improves performance on some benchmarks and
//won't have impact on the overall performance.
bool need64BitEmulation() const {
return m_platformInfo.eProductFamily == IGFX_GEMINILAKE ||
m_platformInfo.eProductFamily == IGFX_BROXTON;
return (m_platformInfo.eProductFamily == IGFX_GEMINILAKE ||
m_platformInfo.eProductFamily == IGFX_BROXTON ||
m_platformInfo.eProductFamily == IGFX_GLENVIEW ||
m_platformInfo.eProductFamily == IGFX_ICELAKE_LP ||
m_platformInfo.eProductFamily == IGFX_LAKEFIELD ||
m_platformInfo.eProductFamily == IGFX_JASPERLAKE);
}
//all the platforms which do not support 64 bit float operations
bool supportFP64() const {
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN7_CORE);
return (m_platformInfo.eRenderCoreFamily >= IGFX_GEN7_CORE &&
m_platformInfo.eProductFamily != IGFX_GLENVIEW &&
m_platformInfo.eProductFamily != IGFX_ICELAKE_LP &&
m_platformInfo.eProductFamily != IGFX_LAKEFIELD &&
m_platformInfo.eProductFamily != IGFX_JASPERLAKE);
}
bool supportLRPInstruction() const { return true; }
bool has8DWA64ScatteredMessage() const { return true; }
bool enableBlendToDiscardAndFill() const { return true; }
bool useOnlyEightPatchDispatchHS() const { return false; }
bool supports256GRFPerThread() const { return false; }
bool hasFDIV() const { return true; }
......@@ -244,8 +288,6 @@ public:
m_platformInfo.eRenderCoreFamily == IGFX_GEN10_CORE));
}
bool DSPrimitiveIDPayloadPhaseCanBeSkipped() const { return false; }
bool HSUsesHWBarriers() const { return false; }
bool applyTEFactorsPadding() const { return false; }
// ***** Below go accessor methods for testing WA data from WA_TABLE *****
bool WaDoNotPushConstantsForAllPulledGSTopologies() const
......
......@@ -68,6 +68,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "Compiler/CISACodeGen/MergeURBWrites.hpp"
#include "Compiler/CISACodeGen/VectorProcess.hpp"
#include "Compiler/CISACodeGen/LowerGEPForPrivMem.hpp"
#include "Compiler/CISACodeGen/POSH_RemoveNonPositionOutput.h"
#include "Compiler/CISACodeGen/SLMConstProp.hpp"
#include "Compiler/Optimizer/OpenCLPasses/PrivateMemory/PrivateMemoryUsageAnalysis.hpp"
......@@ -943,6 +944,10 @@ void unify_opt_PreProcess(CodeGenContext* pContext)
IGCPassManager mpm(pContext, "OPTPre");
mpm.add(new CheckInstrTypes(&(pContext->m_instrTypes)));
if (pContext->isPOSH())
{
mpm.add(createRemoveNonPositionOutputPass());
}
mpm.run(*pContext->getModule());
......
......@@ -541,7 +541,7 @@ bool VectorProcess::runOnFunction(Function& F)
for( inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I )
{