Commit f3442189 authored by Chen, Weiyu's avatar Chen, Weiyu Committed by gbsbuild

clean up mix most inst generation and checks

Change-Id: I57eefb5affddccf54be5e226e88cbb23557b33ce
parent 5931cc3e
......@@ -298,7 +298,6 @@ void G4Verifier::verifyOpnd(G4_Operand* opnd, G4_INST* inst)
}
#endif
// FIXME: If isImm() condition is removed then some assertions are hit.
// This means somewhere in Jitter operand sharing is happening for
// immediate type operands. This should be fixed.
......
......@@ -172,7 +172,7 @@ bool Is_Type_Included(G4_Type type1, G4_Type type2, const IR_Builder& builder)
{
return true;
}
else if (type1 == builder.getMixModeType() && type2 == Type_F )
else if (builder.hasMixMode() && type1 == builder.getMixModeType() && type2 == Type_F )
{
return true;
}
......@@ -1485,7 +1485,6 @@ G4_INST::MovType G4_INST::canPropagate()
G4_Operand *src = srcs[0];
if (src->isRelocImm())
{
return SuperMov;
......@@ -1802,12 +1801,26 @@ bool G4_INST::canPropagateTo(G4_INST *useInst, Gen4_Operand_Number opndNum, MovT
{
return false;
}
//disabling mixMode for MATH instruction
if (isMixedMode() && useInst->isMath())
if (isMixedMode())
{
return false;
if (getExecSize() > 8 || useInst->getExecSize() > 8)
{
return false;
}
G4_opcode useOp = useInst->opcode();
if (useOp != G4_mov &&
useOp != G4_mul &&
useOp != G4_pseudo_mad &&
useOp != G4_add &&
useOp != G4_sel &&
useOp != G4_cmp)
{
return false;
}
}
// special checks for message desc/extended desc, which must be either a0 or imm
if (useInst->isSend())
......@@ -1873,27 +1886,6 @@ bool G4_INST::canPropagateTo(G4_INST *useInst, Gen4_Operand_Number opndNum, MovT
// FIXME: to add specific checks for other instructions.
G4_opcode useInst_op = useInst->opcode();
// Only few instructions allow hf mixed mode.
if (this->isMixedMode() &&
!(useInst_op == G4_mov ||
useInst_op == G4_mul ||
useInst_op == G4_mad ||
useInst_op == G4_pseudo_mad ||
useInst_op == G4_add ||
useInst_op == G4_sel ||
useInst_op == G4_math))
{
return false;
}
if (this->isMixedMode() &&
execSize < 16 &&
MT == FPDownConvSafe &&
useInst->execSize == 16 &&
!useInst->isMixedMode())
{
return false;
}
if ((useInst_op == G4_line && opndNum == Opnd_src0) ||
((useInst_op == G4_if || useInst_op == G4_while) && !src->isImm() && IS_BTYPE(srcType)) ||
(hasModifier && G4_Inst_Table[useInst_op].instType == InstTypeLogic) ||
......@@ -1949,12 +1941,6 @@ bool G4_INST::canPropagateTo(G4_INST *useInst, Gen4_Operand_Number opndNum, MovT
G4_CmpRelation rel = dst->compareOperand(use);
if (rel != Rel_eq)
{
// TODO: When dst Rel_gt use, we still have chance to copy propagate
// the src by splitting it accordingly.
// E.g.
// mov (16) r3.0<1>:ud ...
// mul (8) r5.0<1>:ud r3.0<8;8,1>:ud ...
// mul (8) r6.0<1>:ud r4.0<8;8,1>:ud ...
return false;
}
......@@ -2157,7 +2143,6 @@ bool G4_INST::canHoist(bool simdBB, const Options *opt)
dstType = dst->getType();
srcType = src->getType();
// no dst type promotion after hoisting
if (!Is_Type_Included(dstType, srcType, builder) ||
// if multi def, src and dst should have the same type size
......@@ -2222,7 +2207,18 @@ bool G4_INST::canHoistTo( G4_INST *defInst, bool simdBB)
if (isMixedMode())
{
if (defInst->isMath())
if (getExecSize() > 8 || defInst->getExecSize() > 8)
{
return false;
}
G4_opcode defOp = defInst->opcode();
if (defOp != G4_mov &&
defOp != G4_mul &&
defOp != G4_pseudo_mad &&
defOp != G4_add &&
defOp != G4_sel &&
defOp != G4_cmp)
{
return false;
}
......@@ -2282,23 +2278,10 @@ bool G4_INST::canHoistTo( G4_INST *defInst, bool simdBB)
return false;
}
if (defInst->isSend()) {
// 'mov' following 'send' could be hoisted if and only if
// - that 'mov' is raw move,
// - that 'mov' is not predicated,
// - dst of 'mov' is aligned to GRF.
// - execution size is 8 or 16.
if (!rawMovInst)
return false;
if (getPredicate() || defInst->getPredicate())
return false;
if (dst->getLeftBound() % G4_GRF_REG_NBYTES != 0)
return false;
#if 0
return (execSize == 8 || execSize == 16 || execSize == 32);
#else
// no def hoisting for sends for now
if (defInst->isSend())
{
return false;
#endif
}
if (defInst->opcode() == G4_mov && defInst->getSrc(0)->isFlag())
......@@ -2328,8 +2311,8 @@ bool G4_INST::canHoistTo( G4_INST *defInst, bool simdBB)
return false;
}
bool same_type_size = ( G4_Type_Table[def_dst->getType()].byteSize == G4_Type_Table[srcType].byteSize );
bool scalarSrc = ( srcs[0]->asSrcRegRegion()->isScalar() );
bool same_type_size = G4_Type_Table[def_dst->getType()].byteSize == G4_Type_Table[srcType].byteSize;
bool scalarSrc = srcs[0]->asSrcRegRegion()->isScalar();
// handle predicated MOV and float def
if( ( getPredicate() && ( execSize > 1 ) && !same_type_size ) ||
( IS_FTYPE( defDstType ) && ( defDstType != srcType ) && ( dstType != srcType ) ) )
......@@ -2413,7 +2396,7 @@ bool G4_INST::canHoistTo( G4_INST *defInst, bool simdBB)
// After (invalid optimization):
// or (8) V100(0,0)<1>:d ...
// or (8) V100(0,4)<1>:d ...
if(defDstType != srcType)
if (defDstType != srcType)
{
if(isRawMov() == false)
{
......@@ -3518,7 +3501,6 @@ void G4_INST::emitDefUse(std::ostream& output)
bool G4_INST::isMixedMode() const
{
bool mixedMode = false;
if (mayExceedTwoGRF())
{
return false;
......@@ -3537,12 +3519,11 @@ bool G4_INST::isMixedMode() const
(getDst()->getType() == builder.getMixModeType() || srcType == builder.getMixModeType()) &&
getDst()->getType() != srcType)
{
mixedMode = true;
break;
return true;
}
}
return mixedMode;
return false;
}
// print r#
......
......@@ -495,8 +495,6 @@ bool HWConformity::fixMathInst(INST_LIST_ITER it, G4_BB *bb)
return false;
}
// SKIP mixed mode instructions which are already handled by fixMixedHFInst.
// covers MATH_INT_DIV, MATH_INT_DIV_QUOT, MATH_INT_DIV_REM
bool isIntDivide = inst->asMathInst()->isMathIntDiv();
bool hasSameOffset = hasSameSubregOffset(inst);
......@@ -985,11 +983,12 @@ bool HWConformity::fixOpndType(INST_LIST_ITER it, G4_BB *bb)
{
continue;
}
if (IS_FTYPE(inst->getSrc(i)->getType()) || IS_VFTYPE(inst->getSrc(i)->getType()))
G4_Type ty = inst->getSrc(i)->getType();
if (IS_TYPE_FLOAT_ALL(ty))
{
has_float = true;
}
else if (!IS_DFTYPE(inst->getSrc(i)->getType()) && !IS_HFTYPE(inst->getSrc(i)->getType()))
else
{
has_int = true;
}
......@@ -7323,29 +7322,29 @@ void HWConformity::fixMixedHFInst( BB_LIST_ITER it )
continue;
}
if (inst->isMath() && (inst->isMixedMode() || builder.getOption(vISA_DisableHFMath)))
if (inst->isMath() && builder.getOption(vISA_DisableHFMath))
{
auto src0 = inst->getSrc(0);
auto src1 = inst->getSrc(1);
auto dst = inst->getDst();
if (src0 && src0->getType() == builder.getMixModeType())
if (src0 && src0->getType() == Type_HF)
{
inst->setSrc(insertMovBefore(instIter, 0, Type_F, bb), 0);
}
if (src1 && src1->getType() == builder.getMixModeType())
if (src1 && src1->getType() == Type_HF)
{
inst->setSrc(insertMovBefore(instIter, 1, Type_F, bb), 1);
}
if (dst && dst->getType() == builder.getMixModeType())
if (dst && dst->getType() == Type_HF)
{
inst->setDest(insertMovAfter(instIter, dst, inst->getExecType2(), bb));
}
continue;
}
if (VISA_WA_CHECK(builder.getPWaTable(), WaSrc1ImmHfNotAllowed) && !inst->isSend())
if (VISA_WA_CHECK(builder.getPWaTable(), WaSrc1ImmHfNotAllowed))
{
G4_Operand *tSrc1 = inst->getSrc(1);
if (tSrc1 && tSrc1->isImm() && tSrc1->getType() == Type_HF)
......@@ -7355,43 +7354,18 @@ void HWConformity::fixMixedHFInst( BB_LIST_ITER it )
}
// Restriction :
// The execution size must be no more than 8 when half-floats are used in source or destination operand.
// ToDO: move this to fixmathinst
if (inst->getExecSize() == 16)
{
if (inst->opcode() == G4_math &&
inst->getDst()->getType() == Type_HF &&
if (inst->opcode() == G4_math &&
inst->getDst()->getType() == Type_HF &&
inst->getSrc(0)->getType() == Type_HF &&
(!inst->getSrc(1) || inst->getSrc(1)->getType() == Type_HF))
{
evenlySplitInst(instIter, bb);
}
}
if (inst->isMath() &&
VISA_WA_CHECK(builder.getPWaTable(), WaDstSubRegNumNotAllowedWithLowPrecPacked))
{
G4_DstRegRegion* dst = inst->getDst();
if (dst &&
dst->getType() == Type_HF &&
dst->getSubRegOff() == 8)
{
helperGenerateTempDst(bb, instIter, inst, 1, Type_HF, Sixteen_Word);
}
}
if (inst->isMath() && inst->isMixedMode())
{
// For `math`, additional GRF alignment checking for non-scalar
// destination.
G4_DstRegRegion* dst = inst->getDst();
if (dst->getType() == Type_F &&
inst->getExecSize() != 1 &&
!builder.isOpndAligned(dst, G4_GRF_REG_NBYTES))
{
helperGenerateTempDst(bb, instIter, inst, 1, Type_F, Sixteen_Word);
}
}
G4_DstRegRegion *dst = inst->getDst();
if (INST_FLOAT_SRC_ONLY(inst->opcode()) && dst && !dst->isNullReg() && isLowPrecisionFloatTy(dst->getType()))
......@@ -7417,12 +7391,10 @@ void HWConformity::fixMixedHFInst( BB_LIST_ITER it )
if (!inst->isMixedMode())
continue;
/*
Checks for mix mode HW conformity violations.
*/
if (getGenxPlatform() >= GENX_CHV)
{
if(checkMixMode(instIter, bb))
if (checkMixMode(instIter, bb))
{
//instruction was split, and new instruction inserted before
//going back to previous instruction to double check it still confirms.
......@@ -7431,112 +7403,6 @@ void HWConformity::fixMixedHFInst( BB_LIST_ITER it )
}
}
if (VISA_WA_CHECK(builder.getPWaTable(), WaDstSubRegNumNotAllowedWithLowPrecPacked) &&
dst &&
dst->getType() == Type_HF &&
dst->getSubRegOff() == 8 &&
inst->getExecSize() == 8)
{
helperGenerateTempDst(bb, instIter, inst, 1, dst->getType());
}
if( inst->isMath() &&
((VISA_WA_CHECK(builder.getPWaTable(), WaDisableMixedModeLog) && inst->asMathInst()->getMathCtrl() == MATH_LOG) ||
(VISA_WA_CHECK(builder.getPWaTable(), WaDisableMixedModeFdiv) && inst->asMathInst()->getMathCtrl() == MATH_FDIV) ||
(VISA_WA_CHECK(builder.getPWaTable(), WaDisableMixedModePow) && inst->asMathInst()->getMathCtrl() == MATH_POW)))
{
if (dst && dst->getType() == Type_HF)
{
helperGenerateTempDst(bb, instIter, inst, 1, Type_F);
}
for (uint8_t i = 0; i < inst->getNumSrc(); ++i)
{
G4_Operand *tOpnd = inst->getSrc(i);
if (tOpnd == NULL || !tOpnd->isSrcRegRegion() ||
tOpnd->asSrcRegRegion()->getType() != Type_HF)
{
continue;
}
inst->setSrc(insertMovBefore(instIter, i, Type_F, bb), i);
}
}
// - In Align1, f16 inputs need to be strided
// math(8) r3<1>:hf r4.0<8;8,1>:f r6.0<8;4,2>:hf
if (inst->isMath())
{
for (uint8_t i = 0; i < inst->getNumSrc(); ++i)
{
G4_Operand *tOpnd = inst->getSrc(i);
if (tOpnd == NULL ||
!tOpnd->isSrcRegRegion() ||
tOpnd->asSrcRegRegion()->getType() != Type_HF ||
!tOpnd->asSrcRegRegion()->isNativePackedSrcRegion())
{
continue;
}
inst->setSrc(insertMovBefore(instIter, i, Type_F, bb), i);
}
}
if (inst->isMath() && inst->getSrc(0)->isImm())
{
bool nullSrc1 = inst->getSrc(1) == nullptr || inst->getSrc(1)->isNullReg();
if (!nullSrc1)
{
inst->setSrc(insertMovBefore(instIter, 0, inst->getSrc(0)->getType(), bb), 0);
}
}
for (uint8_t i = 0; i < inst->getNumSrc(); ++i)
{
G4_Operand *tOpnd = inst->getSrc(i);
if (tOpnd == NULL || !tOpnd->isSrcRegRegion())
continue;
G4_SrcRegRegion *srcOpnd = tOpnd->asSrcRegRegion();
// `math` instruction requires non-scalar float operand to be
// GRF aligned.
if (inst->isMath() &&
srcOpnd->getType() == Type_F &&
!srcOpnd->isScalar() &&
!builder.isOpndAligned(tOpnd, G4_GRF_REG_NBYTES)) {
inst->setSrc(insertMovBefore(instIter, i, Type_F, bb), i);
}
/*
8: Math operations for mixed mode,
- In Align1, f16 inputs need to be strided
math(8) r3<1>:hf r4.0<8;8,1>:f r6.0<8;4,2>:hf
If type is hf, and stride is 1, assume it is packed, generate move with stride 2.
*/
if (inst->isMath() &&
srcOpnd->getType() == Type_HF &&
srcOpnd->getRegion()->horzStride == 1)
{
inst->setSrc(insertMovBefore(instIter, i, Type_F, bb), i);
}
}
/*
10. [DevCHV:A]: When packed f16 is used as destination datatype, the subregister MUST be 0.
*/
if(getGenxPlatform() == GENX_CHV &&
GetStepping() == Step_A &&
dst &&
dst->getHorzStride() ==1 &&
dst->getSubRegOff() != 0)
{
helperGenerateTempDst(bb, instIter, inst, 1, dst->getType());
}
/*
12: [DevCHV, DevSKL]: Indirect Addressing on source is not supported when source and destination data types are mixed float.
*/
......@@ -7557,10 +7423,7 @@ void HWConformity::fixMixedHFInst( BB_LIST_ITER it )
inst->getDst()->getType() == Type_HF &&
inst->getDst()->getHorzStride() == 1)
{
if (VISA_WA_CHECK(builder.getPWaTable(), WaDstSubRegNumNotAllowedWithLowPrecPacked))
inst->getDst()->getBase()->asRegVar()->getDeclare()->setSubRegAlign(Sixteen_Word);
else
inst->getDst()->getBase()->asRegVar()->getDeclare()->setSubRegAlign(Eight_Word);
inst->getDst()->getBase()->asRegVar()->getDeclare()->setSubRegAlign(Eight_Word);
}
}
}
......
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