1. 07 Dec, 2018 6 commits
  2. 06 Dec, 2018 1 commit
  3. 04 Dec, 2018 1 commit
  4. 03 Dec, 2018 9 commits
    • Chen, Weiyu's avatar
      Enable SIMD8 DF IEEE macro for selected platforms · 46a77a71
      Chen, Weiyu authored
      Change-Id: I54fd79f72d7af2504be9be1f7f8ebe2b4d25ec63
    • Grzegorz Kluczek's avatar
      Fix Select flag configuration in EmitPass::emitCmpSADs · 1ddbbe14
      Grzegorz Kluczek authored
      Change-Id: I79b25d1f1a54e09710f38cae9414ed2a49e933e6
    • jsantill's avatar
      This is to support following case in TypesLegalizationPass: · d57096b0
      jsantill authored
      %.fca.0.insert.i = insertvalue %struct.VertexOutput.packed undef, <4 x float> %28, 0, !dbg !194
      %.fca.1.0.insert.i = insertvalue %struct.VertexOutput.packed %.fca.0.insert.i, float %44, 1, 0, !dbg !194
      %.fca.1.1.insert.i = insertvalue %struct.VertexOutput.packed %.fca.1.0.insert.i, float %61, 1, 1, !dbg !194
      %76 = extractvalue %struct.VertexOutput.packed %.fca.1.1.insert.i, 1
      %77 = extractvalue [2 x float] %76, 0
      %78 = extractvalue [2 x float] %76, 1
      For value %76, extractvalue is not extracting the scalar value from the structure, it is rather an intermediate instruction that fetches sub-struct, and relies on %77 and %78 to specify what scalar value to extract exactly from the structure.
      Current implementation doesn't handle this case, as it expects extractvalue instruction to provide all indices to get to the bottom of the structure and retrieve scalar value.
      Fix simply skips extractvalues that don't have all necessary indices specified. Later, when we encounter %77 or %78 we recursively traverse it's sources, seeing previous extractvalue (%76) and aggregating indices along the way. Only then we can retrieve the exact value that was inserted to the structure (%.fca.1.0.insert.i and %.fca.1.1.insert.i in this case
      Change-Id: I232a7f32a563d4b4b206403e1351027fdbb56d85
    • Chen, Weiyu's avatar
      Get rid of a redundant header copy for EOT send in compute shader · 6946e36a
      Chen, Weiyu authored
      Change-Id: I5180cf965e780b43a4a8ec5917620ddc2dfd73e9
    • poyuchen's avatar
      Internal feature · b3b0004f
      poyuchen authored
      Change-Id: I2c67e60a57c4373cc32831ba0b9166c60e0f03b0
    • Chen, Weiyu's avatar
      Clean up createSendInst() by requiring a msgDesc is always passed in · 6b09a242
      Chen, Weiyu authored
      Change-Id: I9f4083dc16781ef20233be8fc6b6c98dad49ed7d
    • jsantill's avatar
      Rafctoring code to allow driver to force SIMD mode in the compute path · e5938b1c
      jsantill authored
      This will compile only that SIMD mode which the driver forces (even if it is not profitable according to our profitability analysis
      Change-Id: Ifeda001b1c1a6a2c1015b94e9c9576ccc5c065c7
    • Andrzej Ratajewski's avatar
      In llvm4 WeakVH tracks the value, but in llvm7 there is a · d91553c7
      Andrzej Ratajewski authored
      seperate structure for this purpose which is called WeakTrackingVH.
      WeakVH is no longer tracking the value in llvm7
      Change-Id: I65b2797d322c195b6d2905c46bdaaae3971d70b5
    • Jacek Jankowski's avatar
      Renaming cl::opts in IGCInstCombiner. The conflicts with registered opts from... · 4e296d7b
      Jacek Jankowski authored
      Renaming cl::opts in IGCInstCombiner. The conflicts with registered opts from llvm's Instruction Combining occur in igc-opt
      Change-Id: Ic6749af595090ea8f7ac85ee026816b86b11dc3b
  5. 30 Nov, 2018 21 commits
  6. 29 Nov, 2018 1 commit
  7. 28 Nov, 2018 1 commit