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  1. 11 Sep, 2022 1 commit
  3. 28 Aug, 2022 4 commits
  5. 25 Aug, 2022 1 commit
    • Abner Chang's avatar
      Maintainers.txt: Update maintainers list · 0ede7cad
      Abner Chang authored 
      

Update package maintainers for below package/arch,

1. RISCV64 Architecture:
   Abner is stepping out from RISC-V stuff for now and hand over edk2 RISC-V
   responsibilities to Sunil.
   Daniel Schaefer is no longer with HPE. Update his email address for
   RISCV64 arch. He will keep helping on RISC-V stuff with his personal
   email.

2. EmbeddedPkg:
   Daniel Schaefer is no longer with HPE. Update his email address for
   EmbeddedPkg.

3. EmulatorPkg and RedfishPkg:
   Nickle Wang is no longer with HPE. Update his email address for
   EmulatorPkg and RedfishPkg packages. He will use the personal email for
   the time being until he gets ready with his next journey.

Signed-off-by: default avatarAbner Chang <abner.chang@amd.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Nickle Wang <nickle@csie.io>
Reviewed-by: default avatarDaniel Schaefer <git@danielschaefer.me>
Reviewed-by: default avatarSunil V L <sunilvl@ventanamicro.com>
Reviewed-by: default avatarNickle Wang <nickle@csie.io>
Reviewed-by: default avatarLeif Lindholm <quic_llindhol@quicinc.com>
      0ede7cad
  7. 24 Aug, 2022 1 commit
  9. 23 Aug, 2022 6 commits
  11. 22 Aug, 2022 1 commit
  13. 19 Aug, 2022 1 commit
  15. 18 Aug, 2022 3 commits
  17. 17 Aug, 2022 1 commit
  19. 16 Aug, 2022 4 commits
  21. 15 Aug, 2022 7 commits
  23. 12 Aug, 2022 1 commit
  25. 10 Aug, 2022 1 commit
  27. 09 Aug, 2022 8 commits
    • Ray Ni's avatar
      CpuPageTableLib: define IA32_PAGE_LEVEL enum type internally · e9e2ecab
      Ray Ni authored 
      

The change doesn't change functionality behavior.

Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      e9e2ecab
    • Ray Ni's avatar
      CpuPageTableLib: Fix bug that wrongly requires extra size for mapping · 927113c8
      Ray Ni authored 
      

With following paging structure to map
  [2M-4K, 2M] as P = 1, RW = 0,
  [2M, 4M]    as P = 1, RW = 1:

PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
                    -> PDE[1](RW = 1)

When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.

But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.

The change fixes the bug.

Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      927113c8
    • Ray Ni's avatar
      CpuPageTableLib: Fix a bug to avoid unnecessary changing to page table · 9f53fd4b
      Ray Ni authored 
      

With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
              \-> PDPTE[1] --> PDE[0-255]

If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as read-only, today's logic unnecessarily changes
the paging structure in 2 aspects:
1. When setting PageTableBaseAddress in the entry, the code clears
    all attributes.
2. Even the ReadWrite bit in parent entry is not set, the code clears
    the ReadWrite bit in the leaf entry.

First change is wrong. It should not change other attributes when
setting the PA.
Second change is unnecessary. Because the parent entry already
declares the whole region as read-only, there is no need to clear
ReadWrite bit in the leaf entry again.

Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      9f53fd4b
    • Ray Ni's avatar
      CpuPageTableLib: Fix parent attributes are not inherited properly · f4c845e4
      Ray Ni authored 
      

With the following paging structure that maps [0, 2G] with ReadWrite
bit set.
PML4[0] --> PDPTE[0] --> PDE[0-255]
              \-> PDPTE[1] --> PDE[0-255]

If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called
to change [0, 2M] as writable, today's logic doesn't inherit the
parent entry's attributes when determining the child entry's
attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit.
But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only.

The change fixes the bug.
If the inheritable attributes in ParentPagingEntry conflicts with the
requested attributes, let the child entries take the parent attributes
and loosen the attribute in the parent entry.

E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as
ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change
PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first.
Then change PDE[0].ReadWrite = 1.

Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      f4c845e4
    • Ray Ni's avatar
      CpuPageTableLib: Avoid treating non-leaf entry as leaf one · c16f02f7
      Ray Ni authored 
      

Today's logic wrongly treats the non-leaf entry as leaf entry and
updates its paging attributes.

The patch fixes the bug to only update paging attributes for
non-present entries or leaf entries.

Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      c16f02f7
    • Ray Ni's avatar
      CpuPageTableLib: Split the page entry when LA is aligned but PA is not · 9cb8974f
      Ray Ni authored 
      

When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.

The patch fixes the bug.

Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      9cb8974f
    • Ray Ni's avatar
      CpuPageTableLib: Refactor the logic · 13a0471b
      Ray Ni authored 
      

The patch replaces
  LinearAddress + Offset == RegionStart
with
  ((LinearAddress + Offset) & RegionMask) == 0

The replace should not cause any behavior change.

Because:
1. In first loop of while when LinearAddress + Offset == RegionStart,
  because the lower "BitStart" bits of RegionStart are all-zero,
  all lower "BitStart" bits of (LinearAddress + Offset) are all-zero.
  Because all lower "BitStart" bits of RegionMask is all-one and
  bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0.

2. In following loops of the while, even RegionStart is increased
  by RegionLength, the lower "BitStart" bits are still all-zero.
  So the two expressions still semantically equal to each other.

Signed-off-by: default avatarRay Ni <ray.ni@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      13a0471b
    • Ray Ni's avatar
      CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in Mask · bf334513
      Ray Ni authored 
      

To reproduce the issue:
  UINTN               PageTable;
  VOID                *Buffer;
  UINTN               PageTableBufferSize;
  IA32_MAP_ATTRIBUTE  Attribute;
  IA32_MAP_ATTRIBUTE  Mask;
  RETURN_STATUS       Status;

  Attribute.Uint64       = 0;
  Mask.Uint64            = 0;
  PageTableBufferSize    = 0;
  PageTable              = 0;
  Buffer                 = NULL;
  Attribute.Bits.Present = 1;
  Attribute.Bits.Nx      = 1;
  Mask.Bits.Present      = 1;
  Mask.Uint64            = MAX_UINT64;

  //
  // Create page table to cover [0, 10M)
  //
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_BUFFER_TOO_SMALL);
  Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize));
  Status = PageTableMap (
             &PageTable, PagingMode, Buffer, &PageTableBufferSize,
             0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS);

  //
  // Change the mapping for [0, 4KB)
  // No change actually. Just clear Nx bit in Mask.
  //
  Mask.Bits.Nx        = 0;
  PageTableBufferSize = 0;

  Status = PageTableMap (
             &PageTable, PagingMode, NULL, &PageTableBufferSize,
             0, (UINT64)SIZE_4KB, &Attribute, &Mask
             );
  ASSERT (Status == RETURN_SUCCESS); // FAIL!!

The root cause is when comparing the existing mapping attributes
against the requested one, Mask is not used but it should be used.

Signed-off-by: default avatarZhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: default avatarRay Ni <ray.ni@intel.com>
Reviewed-by: default avatarEric Dong <eric.dong@intel.com>
      bf334513