Commit 6b272173 authored by Matthias Klose's avatar Matthias Klose

* Update the Linaro support to the 7-2019.01 snapshot.

parent 1c82f324
gcc-7 (7.4.0-11) UNRELEASED; urgency=medium
* Update the Linaro support to the 7-2019.01 snapshot.
-- Matthias Klose <doko@debian.org> Fri, 28 Jun 2019 13:00:59 +0200
gcc-7 (7.4.0-10) unstable; urgency=medium
* Update to SVN 20190628 (r272781) from the gcc-7-branch.
......
# DP: Changes for the Linaro 7-2018.04 snapshot (documentation).
# DP: Changes for the Linaro 7-2019.01 snapshot (documentation).
--- a/src/gcc/doc/install.texi
+++ b/src/gcc/doc/install.texi
......@@ -50,7 +50,7 @@
@emph{Adapteva Epiphany Options}
@gccoptlist{-mhalf-reg-file -mprefer-short-insn-regs @gol
@@ -13967,7 +13966,7 @@ support for the ARMv8.2-A architecture extensions.
@@ -13969,7 +13968,7 @@ support for the ARMv8.2-A architecture extensions.
The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler
support for the ARMv8.1-A architecture extension. In particular, it
......@@ -59,7 +59,7 @@
The value @samp{native} is available on native AArch64 GNU/Linux and
causes the compiler to pick the architecture of the host system. This
@@ -14040,8 +14039,10 @@ across releases.
@@ -14042,8 +14041,10 @@ across releases.
This option is only intended to be useful when developing GCC.
@item -mpc-relative-literal-loads
......@@ -71,7 +71,7 @@
accessed using a single instruction and emitted after each function. This
limits the maximum size of functions to 1MB. This is enabled by default for
@option{-mcmodel=tiny}.
@@ -14080,8 +14081,17 @@ instructions. This is on by default for all possible values for options
@@ -14082,8 +14083,17 @@ instructions. This is on by default for all possible values for options
@item lse
Enable Large System Extension instructions. This is on by default for
@option{-march=armv8.1-a}.
......@@ -89,7 +89,7 @@
@end table
@@ -15095,6 +15105,15 @@ ARMv8.2-A architecture with the optional FP16 instructions extension.
@@ -15097,6 +15107,15 @@ ARMv8.2-A architecture with the optional FP16 instructions extension.
This also enables the features provided by @option{-march=armv8.1-a}
and implies @option{-mfp16-format=ieee}.
......
......@@ -89,4 +89,4 @@ Index: b/src/gcc/LINARO-VERSION
--- a/src/gcc/LINARO-VERSION
+++ /dev/null
@@ -1,1 +0,0 @@
-7.3-2018.04~dev
-Snapshot 7.4-2019.01
# DP: Revert r270684, already applied to the Linaro branch
--- a/src/gcc/testsuite/gcc.target/aarch64/pr90075.c
+++ b/src/gcc/testsuite/gcc.target/aarch64/pr90075.c
@@ -1,21 +0,0 @@
-/* { dg-do compile } */
-/* { dg-additional-options "-O1" } */
-
-typedef struct {
- float one, two;
-} twofloats;
-
-float
-bug (twofloats tf)
-{
- float f1, f2;
- union {
- twofloats tfloats;
- float arr[2];
- } utfloats;
-
- utfloats.tfloats = tf;
- f1 = utfloats.arr[1];
- f2 = __builtin_copysignf (0, f1);
- return f2;
-}
--- a/src/gcc/config/aarch64/iterators.md
+++ b/src/gcc/config/aarch64/iterators.md
@@ -438,8 +438,7 @@
(define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
;; Give the ordinal of the MSB in the mode
-(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")
- (HF "#15") (SF "#31") (DF "#63")])
+(define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
;; Attribute to describe constants acceptable in logical operations
(define_mode_attr lconst [(SI "K") (DI "L")])
@@ -508,7 +507,7 @@
(V8HF "16b") (V2SF "8b")
(V4SF "16b") (V2DF "16b")
(DI "8b") (DF "8b")
- (SI "8b") (SF "8b")])
+ (SI "8b")])
;; Define element mode for each vector mode.
(define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
@@ -649,9 +648,6 @@
;; Double vector types for ALLX.
(define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
-;; Mode with floating-point values replaced by like-sized integers.
-(define_mode_attr V_INT_EQUIV [(DF "DI") (SF "SI")])
-
;; Mode of result of comparison operations.
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
(V4HI "V4HI") (V8HI "V8HI")
--- a/src/gcc/config/aarch64/aarch64.md
+++ b/src/gcc/config/aarch64/aarch64.md
@@ -140,7 +140,6 @@
UNSPEC_RSQRTS
UNSPEC_NZCV
UNSPEC_XPACLRI
- UNSPEC_COPYSIGN
])
(define_c_enum "unspecv" [
@@ -5004,45 +5003,45 @@
;; LDR d2, #(1 << 63)
;; BSL v2.8b, [y], [x]
;;
-;; or another, equivalent, sequence using one of BSL/BIT/BIF. Because
-;; we expect these operations to nearly always operate on
-;; floating-point values, we do not want the operation to be
-;; simplified into a bit-field insert operation that operates on the
-;; integer side, since typically that would involve three inter-bank
-;; register copies. As we do not expect copysign to be followed by
-;; other logical operations on the result, it seems preferable to keep
-;; this as an unspec operation, rather than exposing the underlying
-;; logic to the compiler.
+;; or another, equivalent, sequence using one of BSL/BIT/BIF.
+;; aarch64_simd_bsldf will select the best suited of these instructions
+;; to generate based on register allocation, and knows how to partially
+;; constant fold based on the values of X and Y, so expand through that.
-(define_expand "copysign<GPF:mode>3"
- [(match_operand:GPF 0 "register_operand")
- (match_operand:GPF 1 "register_operand")
- (match_operand:GPF 2 "register_operand")]
+(define_expand "copysigndf3"
+ [(match_operand:DF 0 "register_operand")
+ (match_operand:DF 1 "register_operand")
+ (match_operand:DF 2 "register_operand")]
"TARGET_FLOAT && TARGET_SIMD"
{
- rtx bitmask = gen_reg_rtx (<V_INT_EQUIV>mode);
- emit_move_insn (bitmask, GEN_INT (HOST_WIDE_INT_M1U
- << (GET_MODE_BITSIZE (<MODE>mode) - 1)));
- emit_insn (gen_copysign<mode>3_insn (operands[0], operands[1], operands[2],
- bitmask));
+ rtx mask = gen_reg_rtx (DImode);
+ emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 63));
+ emit_insn (gen_aarch64_simd_bsldf (operands[0], mask,
+ operands[2], operands[1]));
DONE;
}
)
-(define_insn "copysign<GPF:mode>3_insn"
- [(set (match_operand:GPF 0 "register_operand" "=w,w,w,r")
- (unspec:GPF [(match_operand:GPF 1 "register_operand" "w,0,w,r")
- (match_operand:GPF 2 "register_operand" "w,w,0,0")
- (match_operand:<V_INT_EQUIV> 3 "register_operand"
- "0,w,w,X")]
- UNSPEC_COPYSIGN))]
+;; As above, but we must first get to a 64-bit value if we wish to use
+;; aarch64_simd_bslv2sf.
+
+(define_expand "copysignsf3"
+ [(match_operand:SF 0 "register_operand")
+ (match_operand:SF 1 "register_operand")
+ (match_operand:SF 2 "register_operand")]
"TARGET_FLOAT && TARGET_SIMD"
- "@
- bsl\\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>
- bit\\t%0.<Vbtype>, %2.<Vbtype>, %3.<Vbtype>
- bif\\t%0.<Vbtype>, %1.<Vbtype>, %3.<Vbtype>
- bfxil\\t%<w1>0, %<w1>1, #0, <sizem1>"
- [(set_attr "type" "neon_bsl<q>,neon_bsl<q>,neon_bsl<q>,bfm")]
+{
+ rtx mask = gen_reg_rtx (DImode);
+
+ /* Juggle modes to get us in to a vector mode for BSL. */
+ rtx op1 = lowpart_subreg (V2SFmode, operands[1], SFmode);
+ rtx op2 = lowpart_subreg (V2SFmode, operands[2], SFmode);
+ rtx tmp = gen_reg_rtx (V2SFmode);
+ emit_move_insn (mask, GEN_INT (HOST_WIDE_INT_1U << 31));
+ emit_insn (gen_aarch64_simd_bslv2sf (tmp, mask, op2, op1));
+ emit_move_insn (operands[0], lowpart_subreg (SFmode, tmp, V2SFmode));
+ DONE;
+}
)
;; -------------------------------------------------------------------
This diff is collapsed.
......@@ -14,6 +14,7 @@ series_file ?= $(patchdir)/series
debian_patches = \
svn-updates \
$(if $(with_linaro_branch),gcc-linaro-revert-r270684) \
$(if $(with_linaro_branch),gcc-linaro) \
$(if $(with_linaro_branch),gcc-linaro-no-macros) \
......
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