Andreas Boll · Michel Dänzer · Andreas Boll · Michel Dänzer · Andreas Boll · Michel Dänzer
--- a/configure.ac
+++ b/configure.ac
@@ -138,12 +138,22 @@ if test "x$GLAMOR" != "xno"; then
 					 [Have glamor_egl_destroy_textured_pixmap API])], [],
 			      [#include "xorg-server.h"
 			       #include "glamor.h"])
+
+		AC_CHECK_DECL(glamor_finish,
+			      [AC_DEFINE(HAVE_GLAMOR_FINISH, 1,
+					 [Have glamor_finish API])],
+					 [PKG_CHECK_MODULES(LIBGL, [gl])],
+			      [#include "xorg-server.h"
+			       #include "glamor.h"])
 	fi

 	if test "x$GLAMOR_XSERVER" != xyes; then
 		PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0])
 		PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
 	fi
+
+	PKG_CHECK_MODULES(GBM, [gbm >= 10.6])
+
 	AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
 else
 	AC_MSG_RESULT([$GLAMOR])

--- a/debian/changelog
+++ b/debian/changelog
 xserver-xorg-video-ati (1:18.0.1-2) UNRELEASED; urgency=medium

+  [ Timo Aaltonen ]
  * Switch to dbgsym packages.

+  [ Andreas Boll ]
+  * Merge upstream patches to fix a blank / corrupted screen with glamor
+    acceleration (Closes: #902965, #904995, #905395, #905960).
+    - 3dcfce8d Bail from dri2_create_buffer2 if we can't get a pixmap
+    - 65c9dfea glamor: Bail CreatePixmap on unsupported pixmap depth
+    - 25836375 Drop unused drmmode_create_bo_pixmap surface parameter
+    - ac18a993 EXA: Remove old RADEONEXACreatePixmap hook
+    - eec4a419 Only initialize libdrm_radeon surface manager for >= R600
+    - ba5d5402 glamor: Don't store radeon_surfaces in pixmaps
+    - 5da2bf43 Factor out radeon_surface_initialize helper
+    - 90b94d40 Move flush from radeon_scanout_do_update to its callers
+    - 6c986e99 Remove throttling from radeon_dri2_copy_region2
+    - 37ba075b Refactor radeon_finish helper
+    - b85b7b11 Add struct radeon_buffer
+    - 3c4c0213 glamor: Use GBM for BO allocation when possible
+    - 499d2f9d glamor: Invalidate cached GEM handle in radeon_set_pixmap_bo
+    - Build-depend on libgbm-dev
+  * Set source format to 1.0.
+  * Update a bunch of URLs in packaging to https.
+  * Bump standards version to 4.2.0.
+
 -- Timo Aaltonen <tjaalton@debian.org>  Wed, 27 Jun 2018 12:48:44 +0300

 xserver-xorg-video-ati (1:18.0.1-1) unstable; urgency=medium

--- a/debian/control
+++ b/debian/control
@@ -13,6 +13,7 @@ Build-Depends:
 x11proto-core-dev,
 x11proto-video-dev,
 libgl1-mesa-dev | libgl-dev,
+ libgbm-dev,
 x11proto-fonts-dev,
 x11proto-randr-dev (>= 1.2),
 x11proto-render-dev,
@@ -21,7 +22,7 @@ Build-Depends:
 x11proto-xf86dri-dev,
 libudev-dev [linux-any],
 xutils-dev (>= 1:7.5+4)
-Standards-Version: 4.1.3
+Standards-Version: 4.2.0
 Vcs-Git: https://salsa.debian.org/xorg-team/driver/xserver-xorg-video-ati.git
 Vcs-Browser: https://salsa.debian.org/xorg-team/driver/xserver-xorg-video-ati.git
 Homepage: https://wiki.freedesktop.org/xorg/RadeonFeature/
@@ -49,7 +50,7 @@ Description: X.Org X server -- AMD/ATI display driver wrapper
 instead of relying on autodetection.
 .
 More information about X.Org can be found at:
- <URL:http://www.X.org>
+ <URL:https://www.X.org>
 .
 This package is built from the X.org xf86-video-ati driver module.

@@ -73,6 +74,6 @@ Description: X.Org X server -- AMD/ATI Radeon display driver
 PITCAIRN, VERDE, OLAND, HAINAN, BONAIRE, KABINI, MULLINS, KAVERI, HAWAII.
 .
 More information about X.Org can be found at:
- <URL:http://www.X.org>
+ <URL:https://www.X.org>
 .
 This package is built from the X.org xf86-video-ati driver module.
--- a/debian/copyright
+++ b/debian/copyright
 This package was downloaded from
-http://xorg.freedesktop.org/releases/individual/driver/
+https://xorg.freedesktop.org/releases/individual/driver/

 Copyright 1997 through 2004 by Marc Aurele La France (TSI @ UQV), tsi@xfree86.org


--- a/debian/rules
+++ b/debian/rules
@@ -14,8 +14,8 @@ override_dh_install:

 # Debug packages:
 override_dh_strip:
-	dh_strip -p$(XXV)-ati    --dbgsym-migration="$(XXV)-ati-dbg (<< 18.0.1-2~)"
-	dh_strip -p$(XXV)-radeon --dbgsym-migration="$(XXV)-radeon-dbg (<< 18.0.1-2~)"
+	dh_strip -p$(XXV)-ati    --dbgsym-migration="$(XXV)-ati-dbg (<< 1:18.0.1-2~)"
+	dh_strip -p$(XXV)-radeon --dbgsym-migration="$(XXV)-radeon-dbg (<< 1:18.0.1-2~)"

 # That's a plugin, use appropriate warning level:
 override_dh_shlibdeps:

--- a/debian/source/format
+++ b/debian/source/format
+1.0
--- a/debian/watch
+++ b/debian/watch
 #git=git://anongit.freedesktop.org/xorg/driver/xf86-video-ati
 version=3
 opts=pgpsigurlmangle=s/$/.sig/ \
-http://xorg.freedesktop.org/releases/individual/driver/ xf86-video-ati-(.*)\.tar\.gz
+https://xorg.freedesktop.org/releases/individual/driver/ xf86-video-ati-(.*)\.tar\.gz
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -62,8 +62,8 @@ radeon_drv_la_SOURCES = \
 	$(RADEON_KMS_SRCS)

 if GLAMOR
-AM_CFLAGS += @LIBGLAMOR_CFLAGS@
-radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@
+AM_CFLAGS += @LIBGLAMOR_CFLAGS@ @GBM_CFLAGS@
+radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ @GBM_LIBS@
 radeon_drv_la_SOURCES += \
 	 radeon_glamor_wrappers.c \
 	 radeon_glamor.c

--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -111,13 +111,11 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
 					  int width, int height,
 					  int depth, int bpp,
 					  int pitch,
-					  struct radeon_bo *bo, struct radeon_surface *psurf)
+					  struct radeon_buffer *bo)
 {
 	RADEONInfoPtr info = RADEONPTR(pScrn);
 	ScreenPtr pScreen = pScrn->pScreen;
 	PixmapPtr pixmap;
-	struct radeon_surface *surface;
-	uint32_t tiling;

 	pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth,
 					  RADEON_CREATE_PIXMAP_SCANOUT);
@@ -135,48 +133,16 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
 	if (!radeon_set_pixmap_bo(pixmap, bo))
 		goto fail;

-	if (info->ChipFamily >= CHIP_FAMILY_R600) {
-		surface = radeon_get_pixmap_surface(pixmap);
-		if (surface && psurf) 
-			*surface = *psurf;
-		else if (surface) {
-			memset(surface, 0, sizeof(struct radeon_surface));
-			surface->npix_x = width;
-			surface->npix_y = height;
-			surface->npix_z = 1;
-			surface->blk_w = 1;
-			surface->blk_h = 1;
-			surface->blk_d = 1;
-			surface->array_size = 1;
-			surface->last_level = 0;
-			surface->bpe = bpp / 8;
-			surface->nsamples = 1;
-			surface->flags = RADEON_SURF_SCANOUT;
-			/* we are requiring a recent enough libdrm version */
-			surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-			surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-			surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-			tiling = radeon_get_pixmap_tiling_flags(pixmap);
-			if (tiling & RADEON_TILING_MICRO) {
-				surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-				surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-			}
-			if (tiling & RADEON_TILING_MACRO) {
-				surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-				surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-			}
-			if (radeon_surface_best(info->surf_man, surface)) {
-				goto fail;
-			}
-			if (radeon_surface_init(info->surf_man, surface)) {
+	if (info->surf_man && !info->use_glamor) {
+		struct radeon_surface *surface = radeon_get_pixmap_surface(pixmap);
+
+		if (!radeon_surface_initialize(info, surface, width, height, bpp / 8,
+					       radeon_get_pixmap_tiling_flags(pixmap), 0))
 			goto fail;
 	}
-		}
-	}

 	if (!info->use_glamor ||
-	    radeon_glamor_create_textured_pixmap(pixmap,
-						 radeon_get_pixmap_private(pixmap)))
+	    radeon_glamor_create_textured_pixmap(pixmap, bo))
 		return pixmap;

 fail:
@@ -412,7 +378,7 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
 	RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
 	RADEONInfoPtr info = RADEONPTR(pScrn);
 	PixmapPtr pixmap = info->fbcon_pixmap;
-	struct radeon_bo *bo;
+	struct radeon_buffer *bo;
 	drmModeFBPtr fbcon;
 	struct drm_gem_flink flink;

@@ -435,18 +401,26 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
 		goto out_free_fb;
 	}

-	bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
+	bo = calloc(1, sizeof(struct radeon_buffer));
+	if (!bo) {
+		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+			   "Couldn't allocate BO for fbcon handle\n");
+		goto out_free_fb;
+	}
+	bo->ref_count = 1;
+
+	bo->bo.radeon = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
 	if (bo == NULL) {
 		xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-			   "Couldn't allocate bo for fbcon handle\n");
+			   "Couldn't open BO for fbcon handle\n");
 		goto out_free_fb;
 	}

 	pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
 					  fbcon->depth, fbcon->bpp, fbcon->pitch,
-					  bo, NULL);
+					  bo);
 	info->fbcon_pixmap = pixmap;
-	radeon_bo_unref(bo);
+	radeon_buffer_unref(&bo);
 out_free_fb:
 	drmModeFreeFB(fbcon);
 	return pixmap;
@@ -460,8 +434,14 @@ destroy_pixmap_for_fbcon(ScrnInfoPtr pScrn)
 	/* XXX: The current GPUVM support in the kernel doesn't allow removing
 	 * the virtual address range for this BO, so we need to keep around
 	 * the pixmap to avoid breaking glamor with GPUVM
+	 *
+	 * Similarly, need to keep around the pixmap with current glamor, to
+	 * avoid issues due to a GEM handle lifetime conflict between us and
+	 * Mesa
 	 */
-	if (info->use_glamor && info->ChipFamily >= CHIP_FAMILY_CAYMAN)
+	if (info->use_glamor &&
+	    (info->ChipFamily >= CHIP_FAMILY_CAYMAN ||
+	     xorgGetVersion() >= XORG_VERSION_NUMERIC(1,19,99,1,0)))
 		return;

 	if (info->fbcon_pixmap)
@@ -529,11 +509,7 @@ drmmode_crtc_scanout_destroy(drmmode_ptr drmmode,
 		scanout->pixmap = NULL;
 	}

-	if (scanout->bo) {
-		radeon_bo_unmap(scanout->bo);
-		radeon_bo_unref(scanout->bo);
-		scanout->bo = NULL;
-	}
+	radeon_buffer_unref(&scanout->bo);
 }

 void
@@ -581,7 +557,7 @@ drmmode_crtc_scanout_create(xf86CrtcPtr crtc, struct drmmode_scanout *scanout,
 						 width, height,
 						 pScrn->depth,
 						 pScrn->bitsPerPixel,
-						 pitch, scanout->bo, NULL);
+						 pitch, scanout->bo);
 	if (!scanout->pixmap) {
 		ErrorF("failed to create CRTC scanout pixmap\n");
 		goto error;
@@ -759,8 +735,7 @@ drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
 					  gc, 0, 0, mode->HDisplay, mode->VDisplay,
 					  0, 0);
 			FreeScratchGC(gc);
-			radeon_cs_flush_indirect(scrn);
-			radeon_bo_wait(drmmode_crtc->scanout[0].bo);
+			radeon_finish(scrn, drmmode_crtc->scanout[0].bo);
 		}
 	}

@@ -818,7 +793,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
 		radeon_scanout_do_update(crtc, scanout_id,
 					 screen->GetWindowPixmap(screen->root),
 					 *box);
-		radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
+		radeon_finish(scrn, drmmode_crtc->scanout[scanout_id].bo);
 	}
 }

@@ -947,7 +922,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
 			fb = radeon_fb_create(pScrn, pRADEONEnt->fd,
 					      pScrn->virtualX, pScrn->virtualY,
 					      pScrn->displayWidth * info->pixel_bytes,
-					      info->front_bo->handle);
+					      info->front_buffer->bo.radeon->handle);
 			/* Prevent refcnt of ad-hoc FBs from reaching 2 */
 			drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL);
 			drmmode_crtc->fb = fb;
@@ -2266,118 +2241,48 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 {
 	xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
 	RADEONInfoPtr info = RADEONPTR(scrn);
-	struct radeon_bo *old_front = NULL;
+	struct radeon_buffer *old_front = NULL;
 	ScreenPtr   screen = xf86ScrnToScreen(scrn);
 	int	    i, pitch, old_width, old_height, old_pitch;
-	int aligned_height;
-	uint32_t screen_size;
+	int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP;
 	int cpp = info->pixel_bytes;
-	struct radeon_bo *front_bo;
-	struct radeon_surface surface;
-	struct radeon_surface *psurface;
-	uint32_t tiling_flags = 0, base_align;
+	uint32_t tiling_flags;
 	PixmapPtr ppix = screen->GetScreenPixmap(screen);
 	void *fb_shadow;

 	if (scrn->virtualX == width && scrn->virtualY == height)
 		return TRUE;

-	front_bo = info->front_bo;
-	radeon_cs_flush_indirect(scrn);
-
-	if (front_bo)
-		radeon_bo_wait(front_bo);
-
 	if (info->allowColorTiling && !info->shadow_primary) {
-		if (info->ChipFamily >= CHIP_FAMILY_R600) {
-			if (info->allowColorTiling2D) {
-				tiling_flags |= RADEON_TILING_MACRO;
-			} else {
-				tiling_flags |= RADEON_TILING_MICRO;
-			}
-		} else
-			tiling_flags |= RADEON_TILING_MACRO;
-	}
-
-	pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(scrn, cpp, tiling_flags)) * cpp;
-	aligned_height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, tiling_flags));
-	screen_size = RADEON_ALIGN(pitch * aligned_height, RADEON_GPU_PAGE_SIZE);
-	base_align = 4096;
-	if (info->ChipFamily >= CHIP_FAMILY_R600) {
-		memset(&surface, 0, sizeof(struct radeon_surface));
-		surface.npix_x = width;
-		surface.npix_y = height;
-		surface.npix_z = 1;
-		surface.blk_w = 1;
-		surface.blk_h = 1;
-		surface.blk_d = 1;
-		surface.array_size = 1;
-		surface.last_level = 0;
-		surface.bpe = cpp;
-		surface.nsamples = 1;
-		surface.flags = RADEON_SURF_SCANOUT;
-		/* we are requiring a recent enough libdrm version */
-		surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-		surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-		surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-		if (tiling_flags & RADEON_TILING_MICRO) {
-			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-		}
-		if (tiling_flags & RADEON_TILING_MACRO) {
-			surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-		}
-		if (radeon_surface_best(info->surf_man, &surface)) {
-			return FALSE;
-		}
-		if (radeon_surface_init(info->surf_man, &surface)) {
-			return FALSE;
-		}
-		screen_size = surface.bo_size;
-		base_align = surface.bo_alignment;
-		pitch = surface.level[0].pitch_bytes;
-		tiling_flags = 0;
-		switch (surface.level[0].mode) {
-		case RADEON_SURF_MODE_2D:
-			tiling_flags |= RADEON_TILING_MACRO;
-			tiling_flags |= surface.bankw << RADEON_TILING_EG_BANKW_SHIFT;
-			tiling_flags |= surface.bankh << RADEON_TILING_EG_BANKH_SHIFT;
-			tiling_flags |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
-			if (surface.tile_split)
-				tiling_flags |= eg_tile_split(surface.tile_split)
-						<< RADEON_TILING_EG_TILE_SPLIT_SHIFT;
-			break;
-		case RADEON_SURF_MODE_1D:
-			tiling_flags |= RADEON_TILING_MICRO;
-			break;
-		default:
-			break;
-		}
-		info->front_surface = surface;
+		if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D)
+			usage |= RADEON_CREATE_PIXMAP_TILING_MACRO;
+		else
+			usage |= RADEON_CREATE_PIXMAP_TILING_MICRO;
 	}

-	xf86DrvMsg(scrn->scrnIndex, X_INFO,
-		   "Allocate new frame buffer %dx%d stride %d\n",
-		   width, height, pitch / cpp);
+	xf86DrvMsg(scrn->scrnIndex, X_INFO, "Allocate new frame buffer %dx%d\n",
+		   width, height);

 	old_width = scrn->virtualX;
 	old_height = scrn->virtualY;
 	old_pitch = scrn->displayWidth;
-	old_front = info->front_bo;
+	old_front = info->front_buffer;

 	scrn->virtualX = width;
 	scrn->virtualY = height;
-	scrn->displayWidth = pitch / cpp;

-	info->front_bo = radeon_bo_open(info->bufmgr, 0, screen_size, base_align,
-					info->shadow_primary ?
-					RADEON_GEM_DOMAIN_GTT :
-					RADEON_GEM_DOMAIN_VRAM,
-					tiling_flags ? RADEON_GEM_NO_CPU_ACCESS : 0);
-	if (!info->front_bo)
+	info->front_buffer = radeon_alloc_pixmap_bo(scrn, scrn->virtualX,
+						    scrn->virtualY, scrn->depth,
+						    usage, scrn->bitsPerPixel,
+						    &pitch,
+						    &info->front_surface,
+						    &tiling_flags);
+	if (!info->front_buffer)
 		goto fail;

+	scrn->displayWidth = pitch / cpp;
+
+	if (!info->use_glamor) {
 #if X_BYTE_ORDER == X_BIG_ENDIAN
 		switch (cpp) {
 		case 4:
@@ -2392,17 +2297,18 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 			tiling_flags |= RADEON_TILING_SURFACE;
 #endif
 		if (tiling_flags)
-	    radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
+			radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch);
+	}

 	if (!info->r600_shadow_fb) {
-		psurface = radeon_get_pixmap_surface(ppix);
-		*psurface = info->front_surface;
+		if (info->surf_man && !info->use_glamor)
+			*radeon_get_pixmap_surface(ppix) = info->front_surface;
 		screen->ModifyPixmapHeader(ppix,
 					   width, height, -1, -1, pitch, NULL);
 	} else {
-		if (radeon_bo_map(info->front_bo, 1))
+		if (radeon_bo_map(info->front_buffer->bo.radeon, 1))
 			goto fail;
-		fb_shadow = calloc(1, screen_size);
+		fb_shadow = calloc(1, pitch * scrn->virtualY);
 		if (fb_shadow == NULL)
 			goto fail;
 		free(info->fb_shadow);
@@ -2416,13 +2322,12 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 		radeon_glamor_create_screen_resources(scrn->pScreen);

 	if (!info->r600_shadow_fb) {
-		if (!radeon_set_pixmap_bo(ppix, info->front_bo))
+		if (!radeon_set_pixmap_bo(ppix, info->front_buffer))
 			goto fail;
 	}

 	radeon_pixmap_clear(ppix);
-	radeon_cs_flush_indirect(scrn);
-	radeon_bo_wait(info->front_bo);
+	radeon_finish(scrn, info->front_buffer);

 	for (i = 0; i < xf86_config->num_crtc; i++) {
 		xf86CrtcPtr crtc = xf86_config->crtc[i];
@@ -2434,16 +2339,14 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
 				       crtc->rotation, crtc->x, crtc->y);
 	}

-	if (old_front)
-		radeon_bo_unref(old_front);
+	radeon_buffer_unref(&old_front);

-	radeon_kms_update_vram_limit(scrn, screen_size);
+	radeon_kms_update_vram_limit(scrn, pitch * scrn->virtualY);
 	return TRUE;

 fail:
-	if (info->front_bo)
-		radeon_bo_unref(info->front_bo);
-	info->front_bo = old_front;
+	radeon_buffer_unref(&info->front_buffer);
+	info->front_buffer = old_front;
 	scrn->virtualX = old_width;
 	scrn->virtualY = old_height;
 	scrn->displayWidth = old_pitch;
@@ -3283,6 +3186,7 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr client,

 			radeon_scanout_do_update(crtc, scanout_id, new_front,
 						 extents);
+			radeon_cs_flush_indirect(crtc->scrn);

 			drmmode_crtc_wait_pending_event(drmmode_crtc, pRADEONEnt->fd,
 							drmmode_crtc->scanout_update_pending);

--- a/src/drmmode_display.h
+++ b/src/drmmode_display.h
@@ -72,7 +72,7 @@ struct drmmode_fb {
 };

 struct drmmode_scanout {
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
    PixmapPtr pixmap;
    int width, height;
 };

--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -71,7 +71,7 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
    if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("invalid planemask\n"));

-    dst.bo = radeon_get_pixmap_bo(pPix);
+    dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
    dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
    dst.surface = radeon_get_pixmap_surface(pPix);

@@ -466,13 +466,13 @@ EVERGREENPrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,

    accel_state->same_surface = FALSE;

-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.surface = radeon_get_pixmap_surface(pDst);
    src_obj.surface = radeon_get_pixmap_surface(pSrc);
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
-    if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
+    if (src_obj.bo == dst_obj.bo)
 	accel_state->same_surface = TRUE;

    src_obj.width = pSrc->drawable.width;
@@ -1301,7 +1301,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
 	return FALSE;

    if (pSrc) {
-	src_obj.bo = radeon_get_pixmap_bo(pSrc);
+	src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
 	src_obj.surface = radeon_get_pixmap_surface(pSrc);
 	src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
 	src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
@@ -1311,7 +1311,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,
 	src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
    }

-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.surface = radeon_get_pixmap_surface(pDst);
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1325,7 +1325,7 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr pSrcPicture,

    if (pMaskPicture) {
 	if (pMask) {
-	    mask_obj.bo = radeon_get_pixmap_bo(pMask);
+	    mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon;
 	    mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
 	    mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
 	    mask_obj.surface = radeon_get_pixmap_surface(pMask);
@@ -1673,16 +1673,16 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
 	return FALSE;

    driver_priv = exaGetPixmapDriverPrivate(pDst);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
 	return FALSE;

    /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
-    copy_dst = driver_priv->bo;
+    copy_dst = driver_priv->bo->bo.radeon;
    copy_pitch = pDst->devKind;
    if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-	if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+	if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
 	    flush = FALSE;
-	    if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+	    if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
 		!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
 		goto copy;
 	}
@@ -1711,7 +1711,7 @@ EVERGREENUploadToScreen(PixmapPtr pDst, int x, int y, int w, int h,
    dst_obj.height = pDst->drawable.height;
    dst_obj.bpp = bpp;
    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    dst_obj.surface = radeon_get_pixmap_surface(pDst);

@@ -1739,7 +1739,7 @@ copy:
    r = TRUE;
    size = w * bpp / 8;
    dst = copy_dst->ptr;
-    if (copy_dst == driver_priv->bo)
+    if (copy_dst == driver_priv->bo->bo.radeon)
 	dst += y * copy_pitch + x * bpp / 8;
    for (i = 0; i < h; i++) {
 	memcpy(dst + i * copy_pitch, src, size);
@@ -1789,15 +1789,15 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
 	return FALSE;

    driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
 	return FALSE;

    /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
-    copy_src = driver_priv->bo;
+    copy_src = driver_priv->bo->bo.radeon;
    copy_pitch = pSrc->devKind;
    if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-	if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
-	    src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+	if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
+	    src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
 	    if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
 		(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
 		src_domain = 0;
@@ -1806,7 +1806,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
 	}

 	if (!src_domain)
-	    radeon_bo_is_busy(driver_priv->bo, &src_domain);
+	    radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);

 	if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
 	    goto copy;
@@ -1841,7 +1841,7 @@ EVERGREENDownloadFromScreen(PixmapPtr pSrc, int x, int y, int w,
    src_obj.height = pSrc->drawable.height;
    src_obj.bpp = bpp;
    src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
    src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
    src_obj.surface = radeon_get_pixmap_surface(pSrc);

@@ -1883,7 +1883,7 @@ copy:
    }
    r = TRUE;
    w *= bpp / 8;
-    if (copy_src == driver_priv->bo)
+    if (copy_src == driver_priv->bo->bo.radeon)
 	size = y * copy_pitch + x * bpp / 8;
    else
 	size = 0;
@@ -2065,7 +2065,6 @@ EVERGREENDrawInit(ScreenPtr pScreen)
    info->accel_state->exa->MarkSync = EVERGREENMarkSync;
    info->accel_state->exa->WaitMarker = EVERGREENSync;

-    info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
    info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
    info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
    info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;

--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -345,12 +345,10 @@ R600SetAccelState(ScrnInfoPtr pScrn,

 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 				    int depth, int usage_hint, int bitsPerPixel,
 				    int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
-extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p);
 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);

--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -140,7 +140,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
    CLEAR (vs_const_conf);
    CLEAR (ps_const_conf);

-    dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+    dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
    dst_obj.surface = radeon_get_pixmap_surface(pPixmap);


--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -150,7 +150,7 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
    if (!RADEONValidPM(pm, pPix->drawable.bitsPerPixel))
 	RADEON_FALLBACK(("invalid planemask\n"));

-    dst.bo = radeon_get_pixmap_bo(pPix);
+    dst.bo = radeon_get_pixmap_bo(pPix)->bo.radeon;
    dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
    dst.surface = radeon_get_pixmap_surface(pPix);

@@ -534,13 +534,13 @@ R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,

    accel_state->same_surface = FALSE;

-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
    src_obj.surface = radeon_get_pixmap_surface(pSrc);
    dst_obj.surface = radeon_get_pixmap_surface(pDst);
-    if (radeon_get_pixmap_bo(pSrc) == radeon_get_pixmap_bo(pDst))
+    if (src_obj.bo == dst_obj.bo)
 	accel_state->same_surface = TRUE;

    src_obj.width = pSrc->drawable.width;
@@ -1344,7 +1344,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
 	return FALSE;

    if (pSrc) {
-	src_obj.bo = radeon_get_pixmap_bo(pSrc);
+	src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
 	src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
 	src_obj.surface = radeon_get_pixmap_surface(pSrc);
 	src_obj.pitch = exaGetPixmapPitch(pSrc) / (pSrc->drawable.bitsPerPixel / 8);
@@ -1354,7 +1354,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
 	src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
    }

-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    dst_obj.surface = radeon_get_pixmap_surface(pDst);
    dst_obj.pitch = exaGetPixmapPitch(pDst) / (pDst->drawable.bitsPerPixel / 8);
@@ -1368,7 +1368,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,

    if (pMaskPicture) {
 	if (pMask) {
-	    mask_obj.bo = radeon_get_pixmap_bo(pMask);
+	    mask_obj.bo = radeon_get_pixmap_bo(pMask)->bo.radeon;
 	    mask_obj.tiling_flags = radeon_get_pixmap_tiling(pMask);
 	    mask_obj.surface = radeon_get_pixmap_surface(pMask);
 	    mask_obj.pitch = exaGetPixmapPitch(pMask) / (pMask->drawable.bitsPerPixel / 8);
@@ -1700,16 +1700,16 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
 	return FALSE;

    driver_priv = exaGetPixmapDriverPrivate(pDst);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
 	return FALSE;

    /* If we know the BO won't be busy / in VRAM, don't bother with a scratch */
-    copy_dst = driver_priv->bo;
+    copy_dst = driver_priv->bo->bo.radeon;
    copy_pitch = pDst->devKind;
    if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-	if (!radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
+	if (!radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
 	    flush = FALSE;
-	    if (!radeon_bo_is_busy(driver_priv->bo, &dst_domain) &&
+	    if (!radeon_bo_is_busy(driver_priv->bo->bo.radeon, &dst_domain) &&
 		!(dst_domain & RADEON_GEM_DOMAIN_VRAM))
 		goto copy;
 	}
@@ -1741,7 +1741,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
    dst_obj.height = pDst->drawable.height;
    dst_obj.bpp = bpp;
    dst_obj.domain = RADEON_GEM_DOMAIN_VRAM;
-    dst_obj.bo = radeon_get_pixmap_bo(pDst);
+    dst_obj.bo = radeon_get_pixmap_bo(pDst)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
    dst_obj.surface = radeon_get_pixmap_surface(pDst);

@@ -1769,7 +1769,7 @@ copy:
    r = TRUE;
    size = w * bpp / 8;
    dst = copy_dst->ptr;
-    if (copy_dst == driver_priv->bo)
+    if (copy_dst == driver_priv->bo->bo.radeon)
 	dst += y * copy_pitch + x * bpp / 8;
    for (i = 0; i < h; i++) {
        memcpy(dst + i * copy_pitch, src, size);
@@ -1819,15 +1819,15 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
 	return FALSE;

    driver_priv = exaGetPixmapDriverPrivate(pSrc);
-    if (!driver_priv || !driver_priv->bo)
+    if (!driver_priv || !driver_priv->bo->bo.radeon)
 	return FALSE;

    /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
-    copy_src = driver_priv->bo;
+    copy_src = driver_priv->bo->bo.radeon;
    copy_pitch = pSrc->devKind;
    if (!(driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
-	if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
-	    src_domain = radeon_bo_get_src_domain(driver_priv->bo);
+	if (radeon_bo_is_referenced_by_cs(driver_priv->bo->bo.radeon, info->cs)) {
+	    src_domain = radeon_bo_get_src_domain(driver_priv->bo->bo.radeon);
 	    if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
 		(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
 		src_domain = 0;
@@ -1836,7 +1836,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
 	}

 	if (!src_domain)
-	    radeon_bo_is_busy(driver_priv->bo, &src_domain);
+	    radeon_bo_is_busy(driver_priv->bo->bo.radeon, &src_domain);

 	if (src_domain & ~(uint32_t)RADEON_GEM_DOMAIN_VRAM)
 	    goto copy;
@@ -1867,7 +1867,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
    src_obj.height = pSrc->drawable.height;
    src_obj.bpp = bpp;
    src_obj.domain = RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT;
-    src_obj.bo = radeon_get_pixmap_bo(pSrc);
+    src_obj.bo = radeon_get_pixmap_bo(pSrc)->bo.radeon;
    src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
    src_obj.surface = radeon_get_pixmap_surface(pSrc);

@@ -1909,7 +1909,7 @@ copy:
    }
    r = TRUE;
    w *= bpp / 8;
-    if (copy_src == driver_priv->bo)
+    if (copy_src == driver_priv->bo->bo.radeon)
 	size = y * copy_pitch + x * bpp / 8;
    else
 	size = 0;
@@ -2044,7 +2044,6 @@ R600DrawInit(ScreenPtr pScreen)
    info->accel_state->exa->MarkSync = R600MarkSync;
    info->accel_state->exa->WaitMarker = R600Sync;

-    info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
    info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
    info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
    info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;

--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -316,12 +316,10 @@ R600SetAccelState(ScrnInfoPtr pScrn,

 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 				    int depth, int usage_hint, int bitsPerPixel,
 				    int *new_pitch);
 extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
-extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
 extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
 extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr slave, void **handle_p);
 extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);

--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -152,7 +152,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
    CLEAR (vs_conf);
    CLEAR (ps_conf);

-    dst_obj.bo = radeon_get_pixmap_bo(pPixmap);
+    dst_obj.bo = radeon_get_pixmap_bo(pPixmap)->bo.radeon;
    dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
    dst_obj.surface = radeon_get_pixmap_surface(pPixmap);


--- a/src/radeon.h
+++ b/src/radeon.h
@@ -83,6 +83,7 @@
 #include "radeon_dri2.h"
 #include "drmmode_display.h"
 #include "radeon_surface.h"
+#include "radeon_bo_helper.h"

 				/* Render support */
 #ifdef RENDER
@@ -300,16 +301,13 @@ radeon_dirty_src_equals(PixmapDirtyUpdatePtr dirty, PixmapPtr pixmap)
 #define CURSOR_WIDTH_CIK	128
 #define CURSOR_HEIGHT_CIK	128

-
 #ifdef USE_GLAMOR

 struct radeon_pixmap {
-	struct radeon_surface surface;
-
 	uint_fast32_t gpu_read;
 	uint_fast32_t gpu_write;

-	struct radeon_bo *bo;
+	struct radeon_buffer *bo;
 	struct drmmode_fb *fb;

 	uint32_t tiling_flags;
@@ -335,7 +333,7 @@ static inline void radeon_set_pixmap_private(PixmapPtr pixmap, struct radeon_pix


 struct radeon_exa_pixmap_priv {
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
    struct drmmode_fb *fb;
    uint32_t tiling_flags;
    struct radeon_surface surface;
@@ -569,7 +567,7 @@ typedef struct {

    void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 
    struct radeon_2d_state state_2d;
-    struct radeon_bo *front_bo;
+    struct radeon_buffer *front_buffer;
    struct radeon_bo_manager *bufmgr;
    struct radeon_cs_manager *csm;
    struct radeon_cs *cs;
@@ -608,6 +606,8 @@ typedef struct {
    unsigned hwcursor_disabled;

 #ifdef USE_GLAMOR
+    struct gbm_device *gbm;
+
    struct {
 	CreateGCProcPtr SavedCreateGC;
 	RegionPtr (*SavedCopyArea)(DrawablePtr, DrawablePtr, GCPtr, int, int,
@@ -645,6 +645,11 @@ extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
 extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn);

 /* radeon_bo_helper.c */
+extern Bool
+radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
+			  int width, int height, int cpp, uint32_t tiling_flags,
+			  int usage_hint);
+
 extern Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle);

 /* radeon_commonfuncs.c */
@@ -703,27 +708,14 @@ extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn);

 static inline struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix)
 {
-#ifdef USE_GLAMOR
-    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
+    struct radeon_exa_pixmap_priv *driver_priv = exaGetPixmapDriverPrivate(pPix);

-    if (info->use_glamor) {
-	struct radeon_pixmap *priv;
-	priv = radeon_get_pixmap_private(pPix);
-	return priv ? &priv->surface : NULL;
-    } else
-#endif
-    {
-	struct radeon_exa_pixmap_priv *driver_priv;
-	driver_priv = exaGetPixmapDriverPrivate(pPix);
    return &driver_priv->surface;
 }

-    return NULL;
-}
-
 uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix);

-static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
+static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_buffer *bo)
 {
    ScrnInfoPtr scrn = xf86ScreenToScrn(pPix->drawable.pScreen);
    RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn);
@@ -742,7 +734,8 @@ static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
 		if (priv->bo == bo)
 		    return TRUE;

-		radeon_bo_unref(priv->bo);
+		radeon_buffer_unref(&priv->bo);
+		priv->handle_valid = FALSE;
 	    }

 	    drmmode_fb_reference(pRADEONEnt->fd, &priv->fb, NULL);
@@ -754,21 +747,18 @@ static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
 	}

 	if (bo) {
-	    uint32_t pitch;
-
 	    if (!priv) {
 		priv = calloc(1, sizeof (struct radeon_pixmap));
 		if (!priv)
 		    return FALSE;
 	    }

-	    radeon_bo_ref(bo);
+	    radeon_buffer_ref(bo);
 	    priv->bo = bo;
-
-	    radeon_bo_get_tiling(bo, &priv->tiling_flags, &pitch);
 	}

 	radeon_set_pixmap_private(pPix, priv);
+	radeon_get_pixmap_tiling_flags(pPix);
 	return TRUE;
    } else
 #endif /* USE_GLAMOR */
@@ -779,15 +769,14 @@ static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
 	if (driver_priv) {
 	    uint32_t pitch;

-	    if (driver_priv->bo)
-		radeon_bo_unref(driver_priv->bo);
-
+	    radeon_buffer_unref(&driver_priv->bo);
 	    drmmode_fb_reference(pRADEONEnt->fd, &driver_priv->fb, NULL);

-	    radeon_bo_ref(bo);
+	    radeon_buffer_ref(bo);
 	    driver_priv->bo = bo;

-	    radeon_bo_get_tiling(bo, &driver_priv->tiling_flags, &pitch);
+	    radeon_bo_get_tiling(bo->bo.radeon, &driver_priv->tiling_flags,
+				 &pitch);
 	    return TRUE;
 	}

@@ -795,7 +784,7 @@ static inline Bool radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo)
    }
 }

-static inline struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix)
+static inline struct radeon_buffer *radeon_get_pixmap_bo(PixmapPtr pPix)
 {
 #ifdef USE_GLAMOR
    RADEONInfoPtr info = RADEONPTR(xf86ScreenToScrn(pPix->drawable.pScreen));
@@ -905,6 +894,7 @@ radeon_pixmap_get_fb(PixmapPtr pix)
    return *fb_ptr;
 }

+
 #define CP_PACKET0(reg, n)						\
 	(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET1(reg0, reg1)						\
@@ -1013,7 +1003,7 @@ do {									\
 #define EMIT_OFFSET(reg, value, pPix, rd, wd) do {		\
    driver_priv = exaGetPixmapDriverPrivate(pPix);		\
    OUT_RING_REG((reg), (value));				\
-    OUT_RING_RELOC(driver_priv->bo, (rd), (wd));			\
+    OUT_RING_RELOC(driver_priv->bo->bo.radeon, (rd), (wd));	\
    } while(0)

 #define EMIT_READ_OFFSET(reg, value, pPix) EMIT_OFFSET(reg, value, pPix, (RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT), 0)
@@ -1027,7 +1017,7 @@ do {									\
 #define EMIT_COLORPITCH(reg, value, pPix) do {			\
    driver_priv = exaGetPixmapDriverPrivate(pPix);			\
    OUT_RING_REG((reg), value);					\
-    OUT_RING_RELOC(driver_priv->bo, 0, RADEON_GEM_DOMAIN_VRAM);		\
+    OUT_RING_RELOC(driver_priv->bo->bo.radeon, 0, RADEON_GEM_DOMAIN_VRAM);	\
 } while(0)

 static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn)

--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -28,6 +28,37 @@
 #include "radeon_glamor.h"
 #include "radeon_bo_gem.h"

+
+#ifdef USE_GLAMOR
+
+static uint32_t
+radeon_get_gbm_format(int depth, int bitsPerPixel)
+{
+    switch (depth) {
+#ifdef GBM_FORMAT_R8
+    case 8:
+	return GBM_FORMAT_R8;
+#endif
+    case 16:
+	return GBM_FORMAT_RGB565;
+    case 32:
+	return GBM_FORMAT_ARGB8888;
+    case 30:
+	return GBM_FORMAT_XRGB2101010;
+    case 24:
+	if (bitsPerPixel == 32)
+	    return GBM_FORMAT_XRGB8888;
+	/* fall through */
+    default:
+	ErrorF("%s: Unsupported depth/bpp %d/%d\n", __func__, depth,
+	       bitsPerPixel);
+	return ~0U;
+    }
+}
+
+#endif /* USE_GLAMOR */
+
+
 static const unsigned MicroBlockTable[5][3][2] = {
    /*linear  tiled   square-tiled */
    {{32, 1}, {8, 4}, {0, 0}}, /*   8 bits per pixel */
@@ -59,10 +90,93 @@ static Bool RADEONMacroSwitch(int width, int height, int bpp,
    }
 }

+static unsigned eg_tile_split_opp(unsigned tile_split)
+{
+    switch (tile_split) {
+        case 0:     tile_split = 64;    break;
+        case 1:     tile_split = 128;   break;
+        case 2:     tile_split = 256;   break;
+        case 3:     tile_split = 512;   break;
+        default:
+        case 4:     tile_split = 1024;  break;
+        case 5:     tile_split = 2048;  break;
+        case 6:     tile_split = 4096;  break;
+    }
+    return tile_split;
+}
+
+Bool
+radeon_surface_initialize(RADEONInfoPtr info, struct radeon_surface *surface,
+			  int width, int height, int cpp, uint32_t tiling_flags,
+			  int usage_hint)
+{
+	memset(surface, 0, sizeof(struct radeon_surface));
+
+	surface->npix_x = width;
+	/* need to align height to 8 for old kernel */
+	surface->npix_y = RADEON_ALIGN(height, 8);
+	surface->npix_z = 1;
+	surface->blk_w = 1;
+	surface->blk_h = 1;
+	surface->blk_d = 1;
+	surface->array_size = 1;
+	surface->last_level = 0;
+	surface->bpe = cpp;
+	surface->nsamples = 1;
+	if (height < 128) {
+	    /* disable 2d tiling for small surface to work around
+	     * the fact that ddx align height to 8 pixel for old
+	     * obscure reason i can't remember
+	     */
+	    tiling_flags &= ~RADEON_TILING_MACRO;
+	}
+
+	surface->flags = RADEON_SURF_SCANOUT | RADEON_SURF_HAS_TILE_MODE_INDEX |
+	    RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+
+	if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
+	    surface->flags |= RADEON_SURF_ZBUFFER;
+	    surface->flags |= RADEON_SURF_SBUFFER;
+	}
+
+	if ((tiling_flags & RADEON_TILING_MACRO)) {
+	    surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+	} else if ((tiling_flags & RADEON_TILING_MICRO)) {
+	    surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
+	} else
+	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
+
+	if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
+	    surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
+		RADEON_TILING_EG_BANKW_MASK;
+	    surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
+		RADEON_TILING_EG_BANKH_MASK;
+	    surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
+						    RADEON_TILING_EG_TILE_SPLIT_MASK);
+	    if (surface->flags & RADEON_SURF_SBUFFER) {
+		surface->stencil_tile_split =
+		    (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
+		    RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
+	    }
+	    surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
+		RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
+	}
+
+	if (radeon_surface_best(info->surf_man, surface))
+	    return FALSE;
+
+	if (radeon_surface_init(info->surf_man, surface))
+	    return FALSE;
+
+	return TRUE;
+}
+
 /* Calculate appropriate tiling and pitch for a pixmap and allocate a BO that
 * can hold it.
 */
-struct radeon_bo*
+struct radeon_buffer *
 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
 		       int usage_hint, int bitsPerPixel, int *new_pitch,
 		       struct radeon_surface *new_surface, uint32_t *new_tiling)
@@ -73,8 +187,48 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
    int cpp = bitsPerPixel / 8;
    uint32_t tiling = 0, flags = 0;
    struct radeon_surface surface;
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
    int domain = RADEON_GEM_DOMAIN_VRAM;
+
+#ifdef USE_GLAMOR
+    if (info->use_glamor &&
+	!(usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
+	  info->shadow_primary)) {
+	uint32_t bo_use = GBM_BO_USE_RENDERING;
+	uint32_t gbm_format = radeon_get_gbm_format(depth, bitsPerPixel);
+
+	if (gbm_format == ~0U)
+	    return NULL;
+
+	bo = calloc(1, sizeof(struct radeon_buffer));
+	if (!bo)
+	    return NULL;
+
+	bo->ref_count = 1;
+
+	if (bitsPerPixel == pScrn->bitsPerPixel)
+	    bo_use |= GBM_BO_USE_SCANOUT;
+
+	if ((usage_hint == CREATE_PIXMAP_USAGE_BACKING_PIXMAP &&
+	     info->shadow_primary) ||
+	    (usage_hint & 0xffff) == CREATE_PIXMAP_USAGE_SHARED)
+	    bo_use |= GBM_BO_USE_LINEAR;
+
+	bo->bo.gbm = gbm_bo_create(info->gbm, width, height, gbm_format, bo_use);
+	if (!bo->bo.gbm) {
+	    free(bo);
+	    return NULL;
+	}
+
+	bo->flags |= RADEON_BO_FLAGS_GBM;
+
+	if (new_pitch)
+	    *new_pitch = gbm_bo_get_stride(bo->bo.gbm);
+
+	return bo;
+    }
+#endif
+
    if (usage_hint) {
 	if (info->allowColorTiling) {
 	    if (usage_hint & RADEON_CREATE_PIXMAP_TILING_MACRO)
@@ -107,51 +261,12 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
    pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * cpp;
    base_align = drmmode_get_base_align(pScrn, cpp, tiling);
    size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
-    memset(&surface, 0, sizeof(struct radeon_surface));

-    if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
-		if (width) {
-			surface.npix_x = width;
-			/* need to align height to 8 for old kernel */
-			surface.npix_y = RADEON_ALIGN(height, 8);
-			surface.npix_z = 1;
-			surface.blk_w = 1;
-			surface.blk_h = 1;
-			surface.blk_d = 1;
-			surface.array_size = 1;
-			surface.last_level = 0;
-			surface.bpe = cpp;
-			surface.nsamples = 1;
-			if (height < 128) {
-				/* disable 2d tiling for small surface to work around
-				 * the fact that ddx align height to 8 pixel for old
-				 * obscure reason i can't remember
-				 */
-				tiling &= ~RADEON_TILING_MACRO;
-			}
-			surface.flags = RADEON_SURF_SCANOUT;
-			/* we are requiring a recent enough libdrm version */
-			surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-			surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-			surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
-			if ((tiling & RADEON_TILING_MICRO)) {
-				surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-				surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-			}
-			if ((tiling & RADEON_TILING_MACRO)) {
-				surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-				surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-			}
-			if (usage_hint & RADEON_CREATE_PIXMAP_SZBUFFER) {
-				surface.flags |= RADEON_SURF_ZBUFFER;
-				surface.flags |= RADEON_SURF_SBUFFER;
-			}
-			if (radeon_surface_best(info->surf_man, &surface)) {
-				return NULL;
-			}
-			if (radeon_surface_init(info->surf_man, &surface)) {
+    if (width && info->surf_man) {
+	if (!radeon_surface_initialize(info, &surface, width, height, cpp,
+				       tiling, usage_hint))
 	    return NULL;
-			}
+
 	size = surface.bo_size;
 	base_align = surface.bo_alignment;
 	pitch = surface.level[0].pitch_bytes;
@@ -164,6 +279,7 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
 	    tiling |= surface.mtilea << RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
 	    if (surface.tile_split)
 		tiling |= eg_tile_split(surface.tile_split) << RADEON_TILING_EG_TILE_SPLIT_SHIFT;
+	    if (surface.flags & RADEON_SURF_SBUFFER)
 		tiling |= eg_tile_split(surface.stencil_tile_split) << RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
 	    break;
 	case RADEON_SURF_MODE_1D:
@@ -172,23 +288,46 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
 	default:
 	    break;
 	}
-		}
+
+	if (new_surface)
+	    *new_surface = surface;
    }

    if (tiling)
 	flags |= RADEON_GEM_NO_CPU_ACCESS;

-    bo = radeon_bo_open(info->bufmgr, 0, size, base_align,
+    bo = calloc(1, sizeof(struct radeon_buffer));
+    if (!bo)
+	return NULL;
+
+    bo->ref_count = 1;
+    bo->bo.radeon = radeon_bo_open(info->bufmgr, 0, size, base_align,
 				   domain, flags);

-    if (bo && tiling && radeon_bo_set_tiling(bo, tiling, pitch) == 0)
+    if (bo && tiling && radeon_bo_set_tiling(bo->bo.radeon, tiling, pitch) == 0)
 	*new_tiling = tiling;

-    *new_surface = surface;
    *new_pitch = pitch;
    return bo;
 }

+
+/* Flush and wait for the BO to become idle */
+void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo)
+{
+    RADEONInfoPtr info = RADEONPTR(scrn);
+
+    if (info->use_glamor) {
+	radeon_glamor_finish(scrn);
+	return;
+    }
+
+    radeon_cs_flush_indirect(scrn);
+    radeon_bo_wait(bo->bo.radeon);
+}
+
+
 /* Clear the pixmap contents to black */
 void
 radeon_pixmap_clear(PixmapPtr pixmap)
@@ -213,7 +352,7 @@ radeon_pixmap_clear(PixmapPtr pixmap)
 /* Get GEM handle for the pixmap */
 Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
 {
-    struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);
+    struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap);
 #ifdef USE_GLAMOR
    ScreenPtr screen = pixmap->drawable.pScreen;
    ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
@@ -221,8 +360,8 @@ Bool radeon_get_pixmap_handle(PixmapPtr pixmap, uint32_t *handle)
    RADEONInfoPtr info = RADEONPTR(scrn);
 #endif

-    if (bo) {
-	*handle = bo->handle;
+    if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM)) {
+	*handle = bo->bo.radeon->handle;
 	return TRUE;
    }

@@ -305,87 +444,82 @@ Bool radeon_share_pixmap_backing(struct radeon_bo *bo, void **handle_p)
    return TRUE;
 }

-static unsigned eg_tile_split_opp(unsigned tile_split)
-{
-    switch (tile_split) {
-        case 0:     tile_split = 64;    break;
-        case 1:     tile_split = 128;   break;
-        case 2:     tile_split = 256;   break;
-        case 3:     tile_split = 512;   break;
-        default:
-        case 4:     tile_split = 1024;  break;
-        case 5:     tile_split = 2048;  break;
-        case 6:     tile_split = 4096;  break;
-    }
-    return tile_split;
-}
-
 Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
 				      struct radeon_surface *surface)
 {
    ScrnInfoPtr pScrn = xf86ScreenToScrn(ppix->drawable.pScreen);
    RADEONInfoPtr info = RADEONPTR(pScrn);
-    struct radeon_bo *bo;
+    struct radeon_buffer *bo;
    int ihandle = (int)(long)fd_handle;
    uint32_t size = ppix->devKind * ppix->drawable.height;
    Bool ret = FALSE;

-    bo = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
+    bo = (struct radeon_buffer *)calloc(1, sizeof(struct radeon_buffer));
    if (!bo)
 	goto error;

-    memset(surface, 0, sizeof(struct radeon_surface));
+#ifdef USE_GLAMOR
+    if (info->use_glamor) {
+	struct gbm_import_fd_data data;
+	uint32_t bo_use = GBM_BO_USE_RENDERING;

-    ret = radeon_set_pixmap_bo(ppix, bo);
-    if (!ret)
+	data.format = radeon_get_gbm_format(ppix->drawable.depth,
+					    ppix->drawable.bitsPerPixel);
+	if (data.format == ~0U)
 	    goto error;

-    if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
-	uint32_t tiling_flags;
+	bo->ref_count = 1;

-#ifdef USE_GLAMOR
-	if (info->use_glamor) {
-	    tiling_flags = radeon_get_pixmap_private(ppix)->tiling_flags;
-	} else
+	data.fd = ihandle;
+	data.width = ppix->drawable.width;
+	data.height = ppix->drawable.height;
+	data.stride = ppix->devKind;
+
+	if (ppix->drawable.bitsPerPixel == pScrn->bitsPerPixel)
+	    bo_use |= GBM_BO_USE_SCANOUT;
+
+	bo->bo.gbm = gbm_bo_import(info->gbm, GBM_BO_IMPORT_FD, &data, bo_use);
+	if (!bo->bo.gbm)
+	    goto error;
+
+	bo->flags |= RADEON_BO_FLAGS_GBM;
+
+	if (!radeon_glamor_create_textured_pixmap(ppix, bo)) {
+	    radeon_buffer_unref(&bo);
+	    return FALSE;
+	}
+
+	ret = radeon_set_pixmap_bo(ppix, bo);
+	/* radeon_set_pixmap_bo increments ref_count if it succeeds */
+	radeon_buffer_unref(&bo);
+	return ret;
+    }
 #endif
-	{
+
+    bo->bo.radeon = radeon_gem_bo_open_prime(info->bufmgr, ihandle, size);
+    if (!bo)
+        goto error;
+
+    bo->ref_count = 1;
+    ret = radeon_set_pixmap_bo(ppix, bo);
+    if (!ret)
+	goto error;
+
+    if (surface) {
 	struct radeon_exa_pixmap_priv *driver_priv;
+	uint32_t tiling_flags;

 	driver_priv = exaGetPixmapDriverPrivate(ppix);
 	tiling_flags = driver_priv->tiling_flags;
-	}

-	surface->npix_x = ppix->drawable.width;
-	surface->npix_y = ppix->drawable.height;
-	surface->npix_z = 1;
-	surface->blk_w = 1;
-	surface->blk_h = 1;
-	surface->blk_d = 1;
-	surface->array_size = 1;
-	surface->bpe = ppix->drawable.bitsPerPixel / 8;
-	surface->nsamples = 1;
-	/* we are requiring a recent enough libdrm version */
-	surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-	surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-	if (tiling_flags & RADEON_TILING_MACRO)
-	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-	else if (tiling_flags & RADEON_TILING_MICRO)
-	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-	else
-	    surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-	surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
-	surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
-	surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK);
-	surface->stencil_tile_split = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
-	surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
-	if (radeon_surface_best(info->surf_man, surface)) {
-	    ret = FALSE;
-	    goto error;
-	}
-	if (radeon_surface_init(info->surf_man, surface)) {
+	if (!radeon_surface_initialize(info, surface, ppix->drawable.width,
+				       ppix->drawable.height,
+				       ppix->drawable.bitsPerPixel / 8,
+				       tiling_flags, 0)) {
 	    ret = FALSE;
 	    goto error;
 	}
+
 	/* we have to post hack the surface to reflect the actual size
 	   of the shared pixmap */
 	surface->level[0].pitch_bytes = ppix->devKind;
@@ -396,6 +530,6 @@ Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void *fd_handle,
    close(ihandle);
    /* we have a reference from the alloc and one from set pixmap bo,
       drop one */
-    radeon_bo_unref(bo);
+    radeon_buffer_unref(&bo);
    return ret;
 }
--- a/src/radeon_bo_helper.h
+++ b/src/radeon_bo_helper.h
@@ -23,11 +23,31 @@
 #ifndef RADEON_BO_HELPER_H
 #define RADEON_BO_HELPER_H 1

-extern struct radeon_bo*
+#ifdef USE_GLAMOR
+#include <gbm.h>
+#endif
+
+#define RADEON_BO_FLAGS_GBM	0x1
+
+struct radeon_buffer {
+	union {
+#ifdef USE_GLAMOR
+		struct gbm_bo *gbm;
+#endif
+		struct radeon_bo *radeon;
+	} bo;
+	uint32_t ref_count;
+    uint32_t flags;
+};
+
+extern struct radeon_buffer *
 radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
 		       int usage_hint, int bitsPerPixel, int *new_pitch,
 		       struct radeon_surface *new_surface, uint32_t *new_tiling);

+extern void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_buffer *bo);
+
 extern void
 radeon_pixmap_clear(PixmapPtr pixmap);

@@ -57,4 +77,37 @@ static inline PixmapPtr get_drawable_pixmap(DrawablePtr drawable)
 	return drawable->pScreen->GetWindowPixmap((WindowPtr)drawable);
 }

+static inline void
+radeon_buffer_ref(struct radeon_buffer *buffer)
+{
+    buffer->ref_count++;
+}
+
+static inline void
+radeon_buffer_unref(struct radeon_buffer **buffer)
+{
+    struct radeon_buffer *buf = *buffer;
+
+    if (!buf)
+	return;
+
+    if (buf->ref_count > 1) {
+	buf->ref_count--;
+	return;
+    }
+
+#ifdef USE_GLAMOR
+    if (buf->flags & RADEON_BO_FLAGS_GBM) {
+	gbm_bo_destroy(buf->bo.gbm);
+    } else
+#endif
+    {
+	radeon_bo_unmap(buf->bo.radeon);
+	radeon_bo_unref(buf->bo.radeon);
+    }
+
+    free(buf);
+    *buffer = NULL;
+}
+
 #endif /* RADEON_BO_HELPER_H */
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -79,11 +79,12 @@ static DevPrivateKeyRec dri2_window_private_key_rec;
 static Bool
 radeon_get_flink_name(RADEONEntPtr pRADEONEnt, PixmapPtr pixmap, uint32_t *name)
 {
-    struct radeon_bo *bo = radeon_get_pixmap_bo(pixmap);
+    struct radeon_buffer *bo = radeon_get_pixmap_bo(pixmap);
    struct drm_gem_flink flink;

-    if (bo)
-	return radeon_gem_get_kernel_name(bo, name) == 0;
+    if (bo && !(bo->flags & RADEON_BO_FLAGS_GBM) &&
+	radeon_gem_get_kernel_name(bo->bo.radeon, name) == 0)
+	return TRUE;

    if (radeon_get_pixmap_handle(pixmap, &flink.handle)) {
 	if (drmIoctl(pRADEONEnt->fd, DRM_IOCTL_GEM_FLINK, &flink) != 0)
@@ -233,11 +234,13 @@ radeon_dri2_create_buffer2(ScreenPtr pScreen,
 					  flags | RADEON_CREATE_PIXMAP_DRI2);
    }

+    if (!pixmap)
+	return NULL;
+
    buffers = calloc(1, sizeof *buffers);
    if (buffers == NULL)
        goto error;

-    if (pixmap) {
    if (!info->use_glamor) {
 	info->exa_force_create = TRUE;
 	exaMoveInPixmap(pixmap);
@@ -253,17 +256,14 @@ radeon_dri2_create_buffer2(ScreenPtr pScreen,

    if (!radeon_get_flink_name(pRADEONEnt, pixmap, &buffers->name))
 	goto error;
-    }

    privates = calloc(1, sizeof(struct dri2_buffer_priv));
    if (privates == NULL)
        goto error;

    buffers->attachment = attachment;
-    if (pixmap) {
    buffers->pitch = pixmap->devKind;
    buffers->cpp = cpp;
-    }
    buffers->driverPrivate = privates;
    buffers->format = format;
    buffers->flags = 0; /* not tiled */
@@ -275,7 +275,6 @@ radeon_dri2_create_buffer2(ScreenPtr pScreen,

 error:
    free(buffers);
-    if (pixmap)
    (*pScreen->DestroyPixmap)(pixmap);
    return NULL;
 }
@@ -338,9 +337,7 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
    Bool vsync;
    Bool translate = FALSE;
    int off_x = 0, off_y = 0;
-    PixmapPtr dst_ppix;

-    dst_ppix = dst_private->pixmap;
    src_drawable = &src_private->pixmap->drawable;
    dst_drawable = &dst_private->pixmap->drawable;

@@ -357,7 +354,6 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
 	    dst_drawable = DRI2UpdatePrime(drawable, dest_buffer);
 	    if (!dst_drawable)
 		return;
-	    dst_ppix = (PixmapPtr)dst_drawable;
 	    if (dst_drawable != drawable)
 		translate = TRUE;
 	} else
@@ -381,26 +377,7 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
    (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0);
    ValidateGC(dst_drawable, gc);

-    /* If this is a full buffer swap or frontbuffer flush, throttle on the
-     * previous one
-     */
-    if (dst_private->attachment == DRI2BufferFrontLeft) {
-	if (REGION_NUM_RECTS(region) == 1) {
-	    BoxPtr extents = REGION_EXTENTS(pScreen, region);
-
-	    if (extents->x1 == 0 && extents->y1 == 0 &&
-		extents->x2 == drawable->width &&
-		extents->y2 == drawable->height) {
-		struct radeon_bo *bo = radeon_get_pixmap_bo(dst_ppix);
-
-		if (bo)
-		    radeon_bo_wait(bo);
-	    }
-	}
-    }
-
    vsync = info->accel_state->vsync;
-
    /* Driver option "SwapbuffersWait" defines if we vsync DRI2 copy-swaps. */ 
    info->accel_state->vsync = info->swapBuffersWait;
    info->accel_state->force = TRUE;
@@ -743,7 +720,7 @@ radeon_dri2_exchange_buffers(DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPt
 {
    struct dri2_buffer_priv *front_priv = front->driverPrivate;
    struct dri2_buffer_priv *back_priv = back->driverPrivate;
-    struct radeon_bo *front_bo, *back_bo;
+    struct radeon_buffer *front_buffer, *back_buffer;
    ScreenPtr screen;
    RADEONInfoPtr info;
    RegionRec region;
@@ -761,19 +738,19 @@ radeon_dri2_exchange_buffers(DrawablePtr draw, DRI2BufferPtr front, DRI2BufferPt
    back->name = tmp;

    /* Swap pixmap bos */
-    front_bo = radeon_get_pixmap_bo(front_priv->pixmap);
-    back_bo = radeon_get_pixmap_bo(back_priv->pixmap);
-    radeon_set_pixmap_bo(front_priv->pixmap, back_bo);
-    radeon_set_pixmap_bo(back_priv->pixmap, front_bo);
+    front_buffer = radeon_get_pixmap_bo(front_priv->pixmap);
+    back_buffer = radeon_get_pixmap_bo(back_priv->pixmap);
+    radeon_set_pixmap_bo(front_priv->pixmap, back_buffer);
+    radeon_set_pixmap_bo(back_priv->pixmap, front_buffer);

    /* Do we need to update the Screen? */
    screen = draw->pScreen;
    info = RADEONPTR(xf86ScreenToScrn(screen));
-    if (front_bo == info->front_bo) {
-	radeon_bo_ref(back_bo);
-	radeon_bo_unref(info->front_bo);
-	info->front_bo = back_bo;
-	radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), back_bo);
+    if (front_buffer == info->front_buffer) {
+	radeon_buffer_ref(back_buffer);
+	radeon_buffer_unref(&info->front_buffer);
+	info->front_buffer = back_buffer;
+	radeon_set_pixmap_bo(screen->GetScreenPixmap(screen), back_buffer);
    }

    radeon_glamor_exchange_buffers(front_priv->pixmap, back_priv->pixmap);