1. 17 Jan, 2018 3 commits
  2. 11 Jan, 2018 1 commit
    • Add Coffeelake PCI IDs for S Skus · 26f54068
      Add the Coffeelake PCI IDs based on the following kernel patches:
      
      commit b056f8f3d6b900e8afd19f312719160346d263b4
      Author: Anusha Srivatsa <anusha.srivatsa@intel.com>
      Date:   Thu Jun 8 16:41:05 2017 -0700
      
          drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.
      
      Signed-off-by: Liwei Song <liwei.song@windriver.com>
      Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
      Liwei Song authored
  3. 20 Dec, 2017 2 commits
  4. 16 Dec, 2017 1 commit
  5. 09 Nov, 2017 3 commits
  6. 08 Nov, 2017 1 commit
  7. 18 Oct, 2017 1 commit
  8. 12 Oct, 2017 3 commits
  9. 08 Oct, 2017 2 commits
  10. 07 Oct, 2017 1 commit
  11. 06 Oct, 2017 1 commit
  12. 27 Sep, 2017 6 commits
  13. 31 Aug, 2017 1 commit
  14. 30 Aug, 2017 1 commit
  15. 22 Aug, 2017 2 commits
    • sna/gen8+: Discard any blt using a LINEAR buffer that is not 64byte aligned · c8990575
      The bug we discovered back in
      
      commit 3a22b6f6
      Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Date:   Wed Nov 19 15:10:05 2014 +0200
      
          sna: gen8 BLT broken when address has bit 4 set
      
      turns out to be even wider than our initial finding. It is now
      recommended that you avoid using the BLT on LINEAR addresses that are not
      cache-line aligned (64 bytes). You can convert the offset into a
      coordinate offset (provided the address is at least pixel aligned), but
      that remains quite hairy to fit into the current code base. So keep
      saying no to misaligned blits (we either use the 3D engine instead,
      which may end up thrashing the TLBs given the LINEAR layout, or we just
      use the CPU).
      
      The impact of issuing misaligned blits is that the blitter ends up
      performing the blit presuming the aligned address, causing it to end up
      offset (and vary per line).
      
      Reported-by: Lyude Paul <lyude@redhat.com>
      Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
      Chris Wilson authored
    • sna/dri2: Defer the drawable flush · 7534e96f
      Just flag the DRI2 flush to occur on the next callback flush, as per
      normal, instead of manually emitting the batch.
      
      Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
      Chris Wilson authored
  16. 28 Jul, 2017 1 commit
    • sna/dri2: Don't cache allocate-as-scanout flag · 2100efa1
      commit 74c1e45e ("sna/dri2: Look for potential flip targets when
      recreating backbuffers") cached the decision on whether to create the
      new back buffer as a scanout target believing that we would always get
      notified when the DRI2 drawable size changed. However, this is only true
      inside a composited environment where we see a change in the Window's
      pixmap. In a bare environment, we either need to chain into the
      screen->ResizeWindow or check every time whether we think a new
      backbuffer should be pre-allocated for use on the scanout.
      
      Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
      Chris Wilson authored
  17. 18 Jul, 2017 1 commit
  18. 07 Jun, 2017 5 commits
  19. 18 Apr, 2017 1 commit
  20. 10 Apr, 2017 1 commit
  21. 25 Mar, 2017 2 commits