radv: Fix single stage constant flush with merged shaders.

e.g. a VERTEX only flush with tess on Vega should look at the TCS
to see which bits are needed.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1953


Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit fd21ee8b)
Conflicts resolved by Dylan Baker

Conflicts:
	src/amd/vulkan/radv_cmd_buffer.c