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debian/changelog
View file @ fff9842e
mesa (19.1.1-1) UNRELEASED; urgency=medium
* New upstream bugfix release.
* rules: Disable panfrost for now, revisit it again for 19.2. (Closes:
#930879)
* control, rules: Enable vulkan-overlay, add glslang-tools to build-depends.
(Closes: #930945)
-- Timo Aaltonen <tjaalton@debian.org> Thu, 27 Jun 2019 10:41:51 +0300
mesa (19.1.0-1) experimental; urgency=medium
* New upstream release.
......
debian/control
View file @ fff9842e
......@@ -6,6 +6,7 @@ Uploaders: Andreas Boll <aboll@debian.org>
Standards-Version: 4.1.4
Build-Depends:
debhelper (>= 11),
glslang-tools [amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el s390x sparc64 x32],
meson (>= 0.45),
quilt (>= 0.63-8.2~),
pkg-config,
......
debian/mesa-vulkan-drivers.install
View file @ fff9842e
usr/share/vulkan/explicit_layer.d/*.json
usr/share/vulkan/icd.d/*.json
usr/lib/*/libvulkan_*.so
usr/lib/*/libVkLayer_MESA_overlay.so
debian/rules
View file @ fff9842e
......@@ -58,7 +58,7 @@ else
# etnaviv, kmsro, tegra, vc4 and v3d kernel support are only available on armhf and arm64
ifneq (,$(filter $(DEB_HOST_ARCH), armhf arm64))
GALLIUM_DRIVERS += etnaviv, kmsro, lima, panfrost, tegra, vc4, v3d,
GALLIUM_DRIVERS += etnaviv, kmsro, lima, tegra, vc4, v3d,
endif
ifneq (,$(filter $(DEB_HOST_ARCH), amd64 i386 x32))
......@@ -106,6 +106,7 @@ else
# arches where we have LLVM enabled and where the Vulkan loader is built.
ifneq (,$(filter $(DEB_HOST_ARCH), amd64 arm64 armel armhf i386 mips mips64el mipsel powerpc ppc64 ppc64el s390x sparc64))
VULKAN_DRIVERS += amd,
confflags_VULKAN += -Dvulkan-overlay-layer=true
endif
confflags_DIRECT_RENDERING = -Dglx-direct=true
......@@ -146,7 +147,8 @@ confflags += \
$(confflags_EGL) \
$(confflags_GALLIUM) \
$(confflags_GLES) \
$(confflags_OSMESA)
$(confflags_OSMESA) \
$(confflags_VULKAN)
override_dh_clean:
rm -rf .pc
......
docs/relnotes/19.1.0.html
View file @ fff9842e
......@@ -32,7 +32,7 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD.
2a6c3af3a803389183168e449c536304cf03e0f82c4c9333077933543b9d02f3 mesa-19.1.0.tar.xz
</pre>
......
docs/relnotes/19.1.1.html 0 → 100644
View file @ fff9842e
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.1.1 Release Notes / June 25, 2019</h1>
<p>
Mesa 19.1.1 is a bug fix release which fixes bugs found since the 19.1.0 release.
</p>
<p>
Mesa 19.1.1 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110709">Bug 110709</a> - g_glxglvnddispatchfuncs.c and glxglvnd.c fail to build with clang 8.0</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110901">Bug 110901</a> - mesa-19.1.0/src/util/futex.h:82: use of out of scope variable ?</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110902">Bug 110902</a> - mesa-19.1.0/src/broadcom/compiler/vir_opt_redundant_flags.c:104]: (style) Same expression</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110921">Bug 110921</a> - virgl on OpenGL 3.3 host regressed to OpenGL 2.1</li>
</ul>
<h2>Changes</h2>
<p>Alejandro Piñeiro (1):</p>
<ul>
<li>v3d: fix checking twice auf flag</li>
</ul>
<p>Bas Nieuwenhuizen (5):</p>
<ul>
<li>radv: Skip transitions coming from external queue.</li>
<li>radv: Decompress DCC when the image format is not allowed for buffers.</li>
<li>radv: Fix vulkan build in meson.</li>
<li>anv: Fix vulkan build in meson.</li>
<li>meson: Allow building radeonsi with just the android platform.</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>nouveau: fix frees in unsupported IR error paths.</li>
</ul>
<p>Eduardo Lima Mitev (1):</p>
<ul>
<li>freedreno/a5xx: Fix indirect draw max_indices calculation</li>
</ul>
<p>Eric Engestrom (3):</p>
<ul>
<li>util/futex: fix dangling pointer use</li>
<li>glx: fix glvnd pointer types</li>
<li>util/os_file: resize buffer to what was actually needed</li>
</ul>
<p>Gert Wollny (1):</p>
<ul>
<li>virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts</li>
</ul>
<p>Haihao Xiang (1):</p>
<ul>
<li>i965: support UYVY for external import only</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>anv: Set STATE_BASE_ADDRESS upper bounds on gen7</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>docs: Add SHA256 sums for 19.1.0</li>
<li>Update version to 19.1.1</li>
</ul>
<p>Kenneth Graunke (2):</p>
<ul>
<li>glsl: Fix out of bounds read in shader_cache_read_program_metadata</li>
<li>iris: Fix iris_flush_and_dirty_history to actually dirty history.</li>
</ul>
<p>Kevin Strasser (2):</p>
<ul>
<li>gallium/winsys/kms: Fix dumb buffer bpp</li>
<li>st/mesa: Add rgbx handling for fp formats</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>anv: do not parse genxml data without INTEL_DEBUG=bat</li>
<li>intel/dump: fix segfault when the app hasn't accessed the device</li>
</ul>
<p>Mathias Fröhlich (1):</p>
<ul>
<li>egl: Don't add hardware device if there is no render node v2.</li>
</ul>
<p>Richard Thier (1):</p>
<ul>
<li>r300g: restore performance after RADEON_FLAG_NO_INTERPROCESS_SHARING was added</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>freedreno/a6xx: un-swap X24S8_UINT</li>
</ul>
<p>Samuel Pitoiset (4):</p>
<ul>
<li>radv: fix occlusion queries on VegaM</li>
<li>radv: fix VK_EXT_memory_budget if one heap isn't available</li>
<li>radv: fix FMASK expand with SRGB formats</li>
<li>radv: disable viewport clamping even if FS doesn't write Z</li>
</ul>
</div>
</body>
</html>
meson.build
View file @ fff9842e
......@@ -353,12 +353,12 @@ else
with_egl = false
endif
if with_egl and not (with_platform_drm or with_platform_surfaceless)
if with_egl and not (with_platform_drm or with_platform_surfaceless or with_platform_android)
if with_gallium_radeonsi
error('RadeonSI requires drm or surfaceless platform when using EGL')
error('RadeonSI requires the drm, surfaceless or android platform when using EGL')
endif
if with_gallium_virgl
error('Virgl requires drm or surfaceless platform when using EGL')
error('Virgl requires the drm, surfaceless or android platform when using EGL')
endif
endif
......
src/amd/vulkan/meson.build
View file @ fff9842e
......@@ -129,6 +129,13 @@ if with_xlib_lease
radv_flags += '-DVK_USE_PLATFORM_XLIB_XRANDR_EXT'
endif
if with_platform_android
radv_flags += [
'-DVK_USE_PLATFORM_ANDROID_KHR'
]
libradv_files += files('radv_android.c')
endif
libvulkan_radeon = shared_library(
'vulkan_radeon',
[libradv_files, radv_entrypoints, radv_extensions_c, amd_vk_format_table_c, sha1_h, xmlpool_options_h],
......
src/amd/vulkan/radv_cmd_buffer.c
View file @ fff9842e
......@@ -4664,6 +4664,9 @@ static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
assert(src_family == cmd_buffer->queue_family_index ||
dst_family == cmd_buffer->queue_family_index);
if (src_family == VK_QUEUE_FAMILY_EXTERNAL)
return;
if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
return;
......
src/amd/vulkan/radv_device.c
View file @ fff9842e
......@@ -1485,7 +1485,11 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
* Note that the application heap usages are not really accurate (eg.
* in presence of shared buffers).
*/
if (vram_size) {
for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
switch (device->mem_type_indices[i]) {
case RADV_MEM_TYPE_VRAM:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM);
......@@ -1493,11 +1497,10 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
heap_usage;
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
}
if (visible_vram_size) {
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_VRAM_VIS);
......@@ -1505,11 +1508,10 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
heap_usage;
memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
}
if (gtt_size) {
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
heap_usage = device->ws->query_value(device->ws,
RADEON_ALLOCATED_GTT);
......@@ -1517,8 +1519,12 @@ radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
heap_usage;
memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
memoryBudget->heapBudget[heap_index] = heap_budget;
memoryBudget->heapUsage[heap_index] = heap_usage;
break;
default:
break;
}
}
/* The heapBudget and heapUsage values must be zero for array elements
......
src/amd/vulkan/radv_formats.c
View file @ fff9842e
......@@ -547,7 +547,7 @@ static bool radv_is_storage_image_format_supported(struct radv_physical_device *
}
}
static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
{
const struct vk_format_description *desc = vk_format_description(format);
unsigned data_format, num_format;
......@@ -559,6 +559,7 @@ static bool radv_is_buffer_format_supported(VkFormat format, bool *scaled)
num_format = radv_translate_buffer_numformat(desc,
vk_format_get_first_non_void_channel(format));
if (scaled)
*scaled = (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) || (num_format == V_008F0C_BUF_NUM_FORMAT_USCALED);
return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID &&
num_format != ~0;
......
src/amd/vulkan/radv_meta_copy.c
View file @ fff9842e
......@@ -187,6 +187,24 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
&pRegions[r].imageSubresource,
pRegions[r].imageSubresource.aspectMask);
if (!radv_is_buffer_format_supported(img_bsurf.format, NULL)) {
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
.levelCount = 1,
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
.layerCount = pRegions[r].imageSubresource.layerCount,
});
}
img_bsurf.format = vk_format_for_size(vk_format_get_blocksize(img_bsurf.format));
img_bsurf.current_layout = VK_IMAGE_LAYOUT_GENERAL;
}
struct radv_meta_blit2d_buffer buf_bsurf = {
.bs = img_bsurf.bs,
.format = img_bsurf.format,
......@@ -313,6 +331,24 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
&pRegions[r].imageSubresource,
pRegions[r].imageSubresource.aspectMask);
if (!radv_is_buffer_format_supported(img_info.format, NULL)) {
uint32_t queue_mask = radv_image_queue_family_mask(image,
cmd_buffer->queue_family_index,
cmd_buffer->queue_family_index);
MAYBE_UNUSED bool compressed = radv_layout_dcc_compressed(image, layout, queue_mask);
if (compressed) {
radv_decompress_dcc(cmd_buffer, image, &(VkImageSubresourceRange) {
.aspectMask = pRegions[r].imageSubresource.aspectMask,
.baseMipLevel = pRegions[r].imageSubresource.mipLevel,
.levelCount = 1,
.baseArrayLayer = pRegions[r].imageSubresource.baseArrayLayer,
.layerCount = pRegions[r].imageSubresource.layerCount,
});
}
img_info.format = vk_format_for_size(vk_format_get_blocksize(img_info.format));
img_info.current_layout = VK_IMAGE_LAYOUT_GENERAL;
}
struct radv_meta_blit2d_buffer buf_info = {
.bs = img_info.bs,
.format = img_info.format,
......
src/amd/vulkan/radv_meta_fmask_expand.c
View file @ fff9842e
......@@ -24,6 +24,7 @@
#include "radv_meta.h"
#include "radv_private.h"
#include "vk_format.h"
static nir_shader *
build_fmask_expand_compute_shader(struct radv_device *device, int samples)
......@@ -132,7 +133,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(image),
.viewType = radv_meta_get_view_type(image),
.format = image->vk_format,
.format = vk_format_no_srgb(image->vk_format),
.subresourceRange = {
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
.baseMipLevel = 0,
......
src/amd/vulkan/radv_pipeline.c
View file @ fff9842e
......@@ -2711,7 +2711,6 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_render_pass_attachment *attachment = NULL;
uint32_t db_depth_control = 0, db_stencil_control = 0;
uint32_t db_render_control = 0, db_render_override2 = 0;
......@@ -2760,8 +2759,7 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
if (!pCreateInfo->pRasterizationState->depthClampEnable &&
ps->info.info.ps.writes_z) {
if (!pCreateInfo->pRasterizationState->depthClampEnable) {
/* From VK_EXT_depth_range_unrestricted spec:
*
* "The behavior described in Primitive Clipping still applies.
......
src/amd/vulkan/radv_private.h
View file @ fff9842e
......@@ -1456,6 +1456,7 @@ uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *de
int first_non_void);
uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
int first_non_void);
bool radv_is_buffer_format_supported(VkFormat format, bool *scaled);
uint32_t radv_translate_colorformat(VkFormat format);
uint32_t radv_translate_color_numformat(VkFormat format,
const struct vk_format_description *desc,
......
src/amd/vulkan/radv_query.c
View file @ fff9842e
......@@ -40,18 +40,6 @@
static const int pipelinestat_block_size = 11 * 8;
static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10};
static unsigned get_max_db(struct radv_device *device)
{
unsigned num_db = device->physical_device->rad_info.num_render_backends;
MAYBE_UNUSED unsigned rb_mask = device->physical_device->rad_info.enabled_rb_mask;
/* Otherwise we need to change the query reset procedure */
assert(rb_mask == ((1ull << num_db) - 1));
return num_db;
}
static nir_ssa_def *nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag)
{
return nir_i2b(b, nir_iand(b, flags, nir_imm_int(b, flag)));
......@@ -108,6 +96,7 @@ build_occlusion_query_shader(struct radv_device *device) {
* uint64_t dst_offset = dst_stride * global_id.x;
* bool available = true;
* for (int i = 0; i < db_count; ++i) {
* if (enabled_rb_mask & (1 << i)) {
* uint64_t start = src_buf[src_offset + 16 * i];
* uint64_t end = src_buf[src_offset + 16 * i + 8];
* if ((start & (1ull << 63)) && (end & (1ull << 63)))
......@@ -115,6 +104,7 @@ build_occlusion_query_shader(struct radv_device *device) {
* else
* available = false;
* }
* }
* uint32_t elem_size = flags & VK_QUERY_RESULT_64_BIT ? 8 : 4;
* if ((flags & VK_QUERY_RESULT_PARTIAL_BIT) || available) {
* if (flags & VK_QUERY_RESULT_64_BIT)
......@@ -139,7 +129,8 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_variable *start = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "start");
nir_variable *end = nir_local_variable_create(b.impl, glsl_uint64_t_type(), "end");
nir_variable *available = nir_local_variable_create(b.impl, glsl_bool_type(), "available");
unsigned db_count = get_max_db(device);
unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
unsigned db_count = device->physical_device->rad_info.num_render_backends;
nir_ssa_def *flags = radv_load_push_int(&b, 0, "flags");
......@@ -187,6 +178,16 @@ build_occlusion_query_shader(struct radv_device *device) {
nir_ssa_def *current_outer_count = nir_load_var(&b, outer_counter);
radv_break_on_count(&b, outer_counter, nir_imm_int(&b, db_count));
nir_ssa_def *enabled_cond =
nir_iand(&b, nir_imm_int(&b, enabled_rb_mask),
nir_ishl(&b, nir_imm_int(&b, 1), current_outer_count));
nir_if *enabled_if = nir_if_create(b.shader);
enabled_if->condition = nir_src_for_ssa(nir_i2b(&b, enabled_cond));
nir_cf_node_insert(b.cursor, &enabled_if->cf_node);
b.cursor = nir_after_cf_list(&enabled_if->then_list);
nir_ssa_def *load_offset = nir_imul(&b, current_outer_count, nir_imm_int(&b, 16));
load_offset = nir_iadd(&b, input_base, load_offset);
......@@ -1044,7 +1045,7 @@ VkResult radv_CreateQueryPool(
switch(pCreateInfo->queryType) {
case VK_QUERY_TYPE_OCCLUSION:
pool->stride = 16 * get_max_db(device);
pool->stride = 16 * device->physical_device->rad_info.num_render_backends;
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS:
pool->stride = pipelinestat_block_size * 2;
......@@ -1157,12 +1158,17 @@ VkResult radv_GetQueryPoolResults(
}
case VK_QUERY_TYPE_OCCLUSION: {
volatile uint64_t const *src64 = (volatile uint64_t const *)src;
uint32_t db_count = device->physical_device->rad_info.num_render_backends;
uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask;
uint64_t sample_count = 0;
int db_count = get_max_db(device);
available = 1;
for (int i = 0; i < db_count; ++i) {
uint64_t start, end;
if (!(enabled_rb_mask & (1 << i)))
continue;
do {
start = src64[2 * i];
end = src64[2 * i + 1];
......
src/broadcom/compiler/vir_opt_redundant_flags.c
View file @ fff9842e
......@@ -102,7 +102,7 @@ vir_opt_redundant_flags_block(struct v3d_compile *c, struct qblock *block)
vir_for_each_inst(inst, block) {
if (inst->qpu.type != V3D_QPU_INSTR_TYPE_ALU ||
inst->qpu.flags.auf != V3D_QPU_UF_NONE ||
inst->qpu.flags.auf != V3D_QPU_UF_NONE) {
inst->qpu.flags.muf != V3D_QPU_UF_NONE) {
last_flags = NULL;
continue;
}
......
src/compiler/glsl/shader_cache.cpp
View file @ fff9842e
......@@ -165,9 +165,8 @@ shader_cache_read_program_metadata(struct gl_context *ctx,
prog->FragDataIndexBindings->iterate(create_binding_str, &buf);
ralloc_asprintf_append(&buf, "tf: %d ", prog->TransformFeedback.BufferMode);
for (unsigned int i = 0; i < prog->TransformFeedback.NumVarying; i++) {
ralloc_asprintf_append(&buf, "%s:%d ",
prog->TransformFeedback.VaryingNames[i],
prog->TransformFeedback.BufferStride[i]);
ralloc_asprintf_append(&buf, "%s ",
prog->TransformFeedback.VaryingNames[i]);
}
/* SSO has an effect on the linked program so include this when generating
......
src/egl/main/egldevice.c
View file @ fff9842e
......@@ -108,9 +108,9 @@ static int
_eglAddDRMDevice(drmDevicePtr device, _EGLDevice **out_dev)
{
_EGLDevice *dev;
const int wanted_nodes = 1 << DRM_NODE_RENDER | 1 << DRM_NODE_PRIMARY;
if ((device->available_nodes & (1 << DRM_NODE_PRIMARY |
1 << DRM_NODE_RENDER)) == 0)
if ((device->available_nodes & wanted_nodes) != wanted_nodes)
return -1;
dev = _eglGlobal.DeviceList;
......