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bin/.cherry-ignore
View file @ 391b6469
......@@ -15,3 +15,5 @@ c9f54486959716762e6818dabb0a73a8cd46df67 radeonsi: fix regression in indirect in
90819abb56f6b1a0cd4946b13b6caf24fb46e500 radv: fix descriptor pool allocation size
# pick: There is a specific patch for stable branch for this commit.
0d495bec25bd7584de4e988c2b4528c1996bc1d0 radeonsi: NaN should pass kill_if
# pick: This commit reverts 0fa9e6d7b30 which did not land in branch.
aa02d7e8781c25ee18b6da97606300808c84973a Revert "anv/skylake: disable ForceThreadDispatchEnable"
common.py
View file @ 391b6469
......@@ -107,9 +107,6 @@ def AddOptions(opts):
opts.Add(BoolOption('debug', 'DEPRECATED: debug build', 'yes'))
opts.Add(BoolOption('profile', 'DEPRECATED: profile build', 'no'))
opts.Add(BoolOption('quiet', 'DEPRECATED: profile build', 'yes'))
opts.Add(BoolOption('texture_float',
'enable floating-point textures and renderbuffers',
'no'))
opts.Add(BoolOption('swr', 'Build OpenSWR', 'no'))
if host_platform == 'windows':
opts.Add('MSVC_VERSION', 'Microsoft Visual C/C++ version')
debian/changelog
View file @ 391b6469
mesa (18.2.3-1) UNRELEASED; urgency=medium
mesa (18.2.4-1) UNRELEASED; urgency=medium
* New upstream release.
- vulkan: Disable randr lease for libxcb < 1.13 (Closes: #908827,
......
docs/relnotes/18.2.3.html
View file @ 391b6469
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
0e13e2342eae74d8848df23595c4bb4b2f8874c9e1213b8466b1fbfa7ef99375 mesa-18.2.3.tar.gz
e2bf83c17e1abdecb1ee81af22652e27e9aa38f963e95e60f34275cc0376304f mesa-18.2.3.tar.xz
</pre>
......
docs/relnotes/18.2.4.html 0 → 100644
View file @ 391b6469
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.4 Release Notes / October 31, 2018</h1>
<p>
Mesa 18.2.4 is a bug fix release which fixes bugs found since the 18.2.4 release.
</p>
<p>
Mesa 18.2.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107865">Bug 107865</a> - swr fail to build with llvm-libs 6.0.1</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108272">Bug 108272</a> - [polaris10] opencl-mesa: Anything using OpenCL segfaults, XFX Radeon RX 580</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108524">Bug 108524</a> - [RADV] GPU lockup on event synchronization</li>
</ul>
<h2>Changes</h2>
<p>Alex Smith (2):</p>
<ul>
<li>ac/nir: Use context-specific LLVM types</li>
<li>anv: Fix sanitization of stencil state when the depth test is disabled</li>
</ul>
<p>Alok Hota (2):</p>
<ul>
<li>swr/rast: ignore CreateElementUnorderedAtomicMemCpy</li>
<li>swr/rast: fix intrinsic/function for LLVM 7 compatibility</li>
</ul>
<p>Andres Rodriguez (1):</p>
<ul>
<li>radv: fix check for perftest options size</li>
</ul>
<p>Bas Nieuwenhuizen (1):</p>
<ul>
<li>radv: Emit enqueued pipeline barriers on event write.</li>
</ul>
<p>Connor Abbott (2):</p>
<ul>
<li>ac: Introduce ac_build_expand()</li>
<li>ac: Fix loading a dvec3 from an SSBO</li>
</ul>
<p>David McFarland (1):</p>
<ul>
<li>util: Change remaining uint32 cache ids to sha1</li>
</ul>
<p>Dylan Baker (1):</p>
<ul>
<li>meson: don't require libelf for r600 without LLVM</li>
</ul>
<p>Elie Tournier (1):</p>
<ul>
<li>gallium: Correctly handle no config context creation</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>radv: s/abs/fabsf/ for floats</li>
</ul>
<p>Jan Vesely (1):</p>
<ul>
<li>radeonsi: Bump number of allowed global buffers to 32</li>
</ul>
<p>Jason Ekstrand (3):</p>
<ul>
<li>spirv: Use the right bit-size for spec constant ops</li>
<li>blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP</li>
<li>anv: Flag semaphore BOs as external</li>
</ul>
<p>Juan A. Suarez Romero (3):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.3</li>
<li>cherry-ignore: Revert "anv/skylake: disable ForceThreadDispatchEnable"</li>
<li>Update version to 18.2.4</li>
</ul>
<p>Liviu Prodea (1):</p>
<ul>
<li>scons: Put to rest zombie texture_float build option.</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>radeonsi: fix a VGT hang with primitive restart on Polaris10 and later</li>
</ul>
<p>Michel Dänzer (1):</p>
<ul>
<li>loader/dri3: Also wait for front buffer fence if we triggered it</li>
</ul>
<p>Nanley Chery (1):</p>
<ul>
<li>intel/blorp: Define the clear value bounds for HiZ clears</li>
</ul>
<p>Rob Clark (2):</p>
<ul>
<li>freedreno: fix inorder rendering case</li>
<li>freedreno: don't flush when new and old pfb is identical</li>
</ul>
</div>
</body>
</html>
meson.build
View file @ 391b6469
......@@ -1061,14 +1061,6 @@ dep_thread = dependency('threads')
if dep_thread.found() and host_machine.system() != 'windows'
pre_args += '-DHAVE_PTHREAD'
endif
if with_amd_vk or with_gallium_radeonsi or with_gallium_r600 or with_gallium_opencl
dep_elf = dependency('libelf', required : false)
if not dep_elf.found()
dep_elf = cc.find_library('elf')
endif
else
dep_elf = null_dep
endif
dep_expat = dependency('expat')
# this only exists on linux so either this is linux and it will be found, or
# its not linux and and wont
......@@ -1225,6 +1217,16 @@ elif with_amd_vk or with_gallium_radeonsi or with_gallium_swr
error('The following drivers require LLVM: Radv, RadeonSI, SWR. One of these is enabled, but LLVM is disabled.')
endif
if (with_amd_vk or with_gallium_radeonsi or with_gallium_opencl or
(with_gallium_r600 and with_llvm))
dep_elf = dependency('libelf', required : false)
if not dep_elf.found()
dep_elf = cc.find_library('elf')
endif
else
dep_elf = null_dep
endif
dep_glvnd = null_dep
if with_glvnd
dep_glvnd = dependency('libglvnd', version : '>= 0.2.0')
......
src/amd/common/ac_llvm_build.c
View file @ 391b6469
......@@ -515,39 +515,51 @@ ac_build_gather_values(struct ac_llvm_context *ctx,
return ac_build_gather_values_extended(ctx, values, value_count, 1, false, false);
}
/* Expand a scalar or vector to <4 x type> by filling the remaining channels
* with undef. Extract at most num_channels components from the input.
/* Expand a scalar or vector to <dst_channels x type> by filling the remaining
* channels with undef. Extract at most src_channels components from the input.
*/
LLVMValueRef ac_build_expand_to_vec4(struct ac_llvm_context *ctx,
LLVMValueRef ac_build_expand(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned num_channels)
unsigned src_channels,
unsigned dst_channels)
{
LLVMTypeRef elemtype;
LLVMValueRef chan[4];
LLVMValueRef chan[dst_channels];
if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
num_channels = MIN2(num_channels, vec_size);
if (num_channels >= 4)
if (src_channels == dst_channels && vec_size == dst_channels)
return value;
for (unsigned i = 0; i < num_channels; i++)
src_channels = MIN2(src_channels, vec_size);
for (unsigned i = 0; i < src_channels; i++)
chan[i] = ac_llvm_extract_elem(ctx, value, i);
elemtype = LLVMGetElementType(LLVMTypeOf(value));
} else {
if (num_channels) {
assert(num_channels == 1);
if (src_channels) {
assert(src_channels == 1);
chan[0] = value;
}
elemtype = LLVMTypeOf(value);
}
while (num_channels < 4)
chan[num_channels++] = LLVMGetUndef(elemtype);
for (unsigned i = src_channels; i < dst_channels; i++)
chan[i] = LLVMGetUndef(elemtype);
return ac_build_gather_values(ctx, chan, dst_channels);
}
return ac_build_gather_values(ctx, chan, 4);
/* Expand a scalar or vector to <4 x type> by filling the remaining channels
* with undef. Extract at most num_channels components from the input.
*/
LLVMValueRef ac_build_expand_to_vec4(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned num_channels)
{
return ac_build_expand(ctx, value, num_channels, 4);
}
LLVMValueRef
......
src/amd/common/ac_llvm_build.h
View file @ 391b6469
......@@ -161,6 +161,9 @@ LLVMValueRef
ac_build_gather_values(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count);
LLVMValueRef ac_build_expand(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned src_channels, unsigned dst_channels);
LLVMValueRef ac_build_expand_to_vec4(struct ac_llvm_context *ctx,
LLVMValueRef value,
unsigned num_channels);
......
src/amd/common/ac_nir_to_llvm.c
View file @ 391b6469
......@@ -1400,7 +1400,7 @@ static LLVMValueRef visit_load_push_constant(struct ac_nir_context *ctx,
if (instr->dest.ssa.bit_size == 16) {
unsigned load_dwords = instr->dest.ssa.num_components / 2 + 1;
LLVMTypeRef vec_type = LLVMVectorType(LLVMInt16Type(), 2 * load_dwords);
LLVMTypeRef vec_type = LLVMVectorType(LLVMInt16TypeInContext(ctx->ac.context), 2 * load_dwords);
ptr = ac_cast_ptr(&ctx->ac, ptr, vec_type);
LLVMValueRef res = LLVMBuildLoad(ctx->ac.builder, ptr, "");
res = LLVMBuildBitCast(ctx->ac.builder, res, vec_type, "");
......@@ -1673,7 +1673,7 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
};
results[idx] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
unsigned num_elems = ac_get_type_size(data_type) / elem_size_bytes;
LLVMTypeRef resTy = LLVMVectorType(LLVMIntType(instr->dest.ssa.bit_size), num_elems);
LLVMTypeRef resTy = LLVMVectorType(LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size), num_elems);
results[idx] = LLVMBuildBitCast(ctx->ac.builder, results[idx], resTy, "");
}
}
......@@ -1687,8 +1687,8 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
};
if (num_bytes > 16 && num_components == 3) {
/* we end up with a v4f32 and v2f32 but shuffle fails on that */
results[1] = ac_build_expand_to_vec4(&ctx->ac, results[1], 2);
/* we end up with a v2i64 and i64 but shuffle fails on that */
results[1] = ac_build_expand(&ctx->ac, results[1], 1, 2);
}
LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
......
src/amd/vulkan/radv_cmd_buffer.c
View file @ 391b6469
......@@ -4347,6 +4347,8 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(event->bo);
si_emit_cache_flush(cmd_buffer);
radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
......
src/amd/vulkan/radv_device.c
View file @ 391b6469
......@@ -49,24 +49,6 @@
#include "util/debug.h"
#include "util/mesa-sha1.h"
static bool
radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
{
uint32_t timestamp;
#ifdef HAVE_DL_ITERATE_PHDR
const struct build_id_note *note = NULL;
if ((note = build_id_find_nhdr_for_addr(ptr))) {
_mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
} else
#endif
if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
_mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
} else
return false;
return true;
}
static int
radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
{
......@@ -77,8 +59,8 @@ radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
memset(uuid, 0, VK_UUID_SIZE);
_mesa_sha1_init(&ctx);
if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
!radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
!disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
return -1;
_mesa_sha1_update(&ctx, &family, sizeof(family));
......@@ -484,7 +466,7 @@ static const struct debug_control radv_perftest_options[] = {
const char *
radv_get_perftest_option_name(int id)
{
assert(id < ARRAY_SIZE(radv_debug_options) - 1);
assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
return radv_perftest_options[id].string;
}
......
src/amd/vulkan/si_cmd_buffer.c
View file @ 391b6469
......@@ -532,16 +532,16 @@ si_write_scissors(struct radeon_cmdbuf *cs, int first,
VkRect2D scissor = si_intersect_scissor(&scissors[i], &viewport_scissor);
get_viewport_xform(viewports + i, scale, translate);
scale[0] = abs(scale[0]);
scale[1] = abs(scale[1]);
scale[0] = fabsf(scale[0]);
scale[1] = fabsf(scale[1]);
if (scale[0] < 0.5)
scale[0] = 0.5;
if (scale[1] < 0.5)
scale[1] = 0.5;
guardband_x = MIN2(guardband_x, (max_range - abs(translate[0])) / scale[0]);
guardband_y = MIN2(guardband_y, (max_range - abs(translate[1])) / scale[1]);
guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
radeon_emit(cs, S_028250_TL_X(scissor.offset.x) |
S_028250_TL_Y(scissor.offset.y) |
......
src/compiler/spirv/spirv_to_nir.c
View file @ 391b6469
......@@ -1771,11 +1771,17 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
nir_const_value src[4];
for (unsigned i = 0; i < count - 4; i++) {
nir_constant *c =
vtn_value(b, w[4 + i], vtn_value_type_constant)->constant;
struct vtn_value *src_val =
vtn_value(b, w[4 + i], vtn_value_type_constant);
/* If this is an unsized source, pull the bit size from the
* source; otherwise, we'll use the bit size from the destination.
*/
if (!nir_alu_type_get_type_size(nir_op_infos[op].input_types[i]))
bit_size = glsl_get_bit_size(src_val->type->type);
unsigned j = swap ? 1 - i : i;
src[j] = c->values[0];
src[j] = src_val->constant->values[0];
}
val->constant->values[0] =
......
src/gallium/drivers/freedreno/freedreno_state.c
View file @ 391b6469
......@@ -211,6 +211,15 @@ fd_set_framebuffer_state(struct pipe_context *pctx,
struct fd_context *ctx = fd_context(pctx);
struct pipe_framebuffer_state *cso;
cso = &ctx->batch->framebuffer;
if (util_framebuffer_state_equal(cso, framebuffer))
return;
util_copy_framebuffer_state(cso, framebuffer);
cso->samples = util_framebuffer_get_num_samples(cso);
if (ctx->screen->reorder) {
struct fd_batch *batch, *old_batch = NULL;
......@@ -239,14 +248,9 @@ fd_set_framebuffer_state(struct pipe_context *pctx,
DBG("%d: cbufs[0]=%p, zsbuf=%p", ctx->batch->needs_flush,
framebuffer->cbufs[0], framebuffer->zsbuf);
fd_batch_flush(ctx->batch, false, false);
util_copy_framebuffer_state(&ctx->batch->framebuffer, cso);
}
cso = &ctx->batch->framebuffer;
util_copy_framebuffer_state(cso, framebuffer);
cso->samples = util_framebuffer_get_num_samples(cso);
ctx->dirty |= FD_DIRTY_FRAMEBUFFER;
ctx->disabled_scissor.minx = 0;
......
src/gallium/drivers/nouveau/nouveau_screen.c
View file @ 391b6469
......@@ -148,20 +148,21 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
static void
nouveau_disk_cache_create(struct nouveau_screen *screen)
{
uint32_t mesa_id;
char *mesa_id_str;
int res;
if (disk_cache_get_function_identifier(nouveau_disk_cache_create,
&mesa_id)) {
res = asprintf(&mesa_id_str, "%u", mesa_id);
if (res != -1) {
struct mesa_sha1 ctx;
unsigned char sha1[20];
char cache_id[20 * 2 + 1];
_mesa_sha1_init(&ctx);
if (!disk_cache_get_function_identifier(nouveau_disk_cache_create,
&ctx))
return;
_mesa_sha1_final(&ctx, sha1);
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
screen->disk_shader_cache =
disk_cache_create(nouveau_screen_get_name(&screen->base),
mesa_id_str, 0);
free(mesa_id_str);
}
}
cache_id, 0);
}
int
......
src/gallium/drivers/r600/r600_pipe_common.c
View file @ 391b6469
......@@ -854,14 +854,18 @@ static void r600_disk_cache_create(struct r600_common_screen *rscreen)
if (rscreen->debug_flags & DBG_ALL_SHADERS)
return;
uint32_t mesa_id;
if (disk_cache_get_function_identifier(r600_disk_cache_create,
&mesa_id)) {
char *mesa_id_str;
int res = -1;
res = asprintf(&mesa_id_str, "%u", mesa_id);
if (res != -1) {
struct mesa_sha1 ctx;
unsigned char sha1[20];
char cache_id[20 * 2 + 1];
_mesa_sha1_init(&ctx);
if (!disk_cache_get_function_identifier(r600_disk_cache_create,
&ctx))
return;
_mesa_sha1_final(&ctx, sha1);
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
/* These flags affect shader compilation. */
uint64_t shader_debug_flags =
rscreen->debug_flags &
......@@ -870,11 +874,8 @@ static void r600_disk_cache_create(struct r600_common_screen *rscreen)
rscreen->disk_shader_cache =
disk_cache_create(r600_get_family_name(rscreen),
mesa_id_str,
cache_id,
shader_debug_flags);
free(mesa_id_str);
}
}
}
static struct disk_cache *r600_get_disk_shader_cache(struct pipe_screen *pscreen)
......
src/gallium/drivers/radeonsi/si_compute.h
View file @ 391b6469
......@@ -29,7 +29,7 @@
#include "si_shader.h"
#define MAX_GLOBAL_BUFFERS 22
#define MAX_GLOBAL_BUFFERS 32
struct si_compute {
struct pipe_reference reference;
......
src/gallium/drivers/radeonsi/si_pipe.c
View file @ 391b6469
......@@ -751,17 +751,20 @@ static void si_disk_cache_create(struct si_screen *sscreen)
if (sscreen->debug_flags & DBG_ALL_SHADERS)
return;
uint32_t mesa_id;
if (disk_cache_get_function_identifier(si_disk_cache_create, &mesa_id)) {
char *driver_id_str;
int res = -1;
uint32_t llvm_id;
if (disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
&llvm_id)) {
res = asprintf(&driver_id_str, "%u_%u", mesa_id, llvm_id);
}
struct mesa_sha1 ctx;
unsigned char sha1[20];
char cache_id[20 * 2 + 1];
_mesa_sha1_init(&ctx);
if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
!disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
&ctx))
return;
_mesa_sha1_final(&ctx, sha1);
disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
if (res != -1) {
/* These flags affect shader compilation. */
#define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
DBG(SI_SCHED) | \
......@@ -779,11 +782,8 @@ static void si_disk_cache_create(struct si_screen *sscreen)
sscreen->disk_shader_cache =
disk_cache_create(si_get_family_name(sscreen),
driver_id_str,
cache_id,
shader_debug_flags);
free(driver_id_str);
}
}
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
......
src/gallium/drivers/radeonsi/si_state_draw.c
View file @ 391b6469
......@@ -383,7 +383,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
* Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
* for points, line strips, and tri strips.
*/
if (sscreen->info.max_se < 4 ||
if (sscreen->info.max_se <= 2 ||
key->u.prim == PIPE_PRIM_POLYGON ||
key->u.prim == PIPE_PRIM_LINE_LOOP ||
key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
......@@ -414,7 +414,7 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
wd_switch_on_eop = true;
/* Required on CIK and later. */
if (sscreen->info.max_se > 2 && !wd_switch_on_eop)
if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
ia_switch_on_eoi = true;
/* Required by Hawaii and, for some special cases, by VI. */
......@@ -429,6 +429,12 @@ si_get_init_multi_vgt_param(struct si_screen *sscreen,
key->u.uses_instancing)
partial_vs_wave = true;
/* This only applies to Polaris10 and later 4 SE chips.
* wd_switch_on_eop is already true on all other chips.
*/
if (!wd_switch_on_eop && key->u.primitive_restart)
partial_vs_wave = true;
/* If the WD switch is false, the IA switch must be false too. */
assert(wd_switch_on_eop || !ia_switch_on_eop);
}
......