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bin/.cherry-ignore
View file @ 419ee200
......@@ -31,3 +31,9 @@ ac324a6809c09c54d3b0bfdb00e5e62987ec4ad8 intel/aub_viewer: fix dynamic state pri
# fixes: This commit requires commits 854202f70e6 and 84bc5738401 which did not
# land in branch.
c120dbfe4d18240315ecec9b43a61aeb9ab239ac mesa/main: fix incorrect depth-error
# fixes: This commit fixes commits b4476138d5ad and aa0fed10d357 which did not
# land in branch.
d0c7b079d07f751eb37ecaa45a2a6db920d71d7a freedreno: Fix autotools build.
# pick: While this commit does not include the proper CC tag, it was intended
# to be applied only in 18.3 branch.
017199d2d2e4c57015bc60edfcc656062c3a7472 mesa: Revert INTEL_fragment_shader_ordering support
docs/relnotes/18.2.6.html
View file @ 419ee200
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
e0ea1236dbc6c412b02e1b5d7f838072525971a6630246fa82ae4466a6d8a587 mesa-18.2.6.tar.gz
9ebafa4f8249df0c718e93b9ca155e3593a1239af303aa2a8b0f2056a7efdc12 mesa-18.2.6.tar.xz
</pre>
......
docs/relnotes/18.2.7.html 0 → 100644
View file @ 419ee200
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.7 Release Notes / December 13, 2018</h1>
<p>
Mesa 18.2.7 is a bug fix release which fixes bugs found since the 18.2.6 release.
</p>
<p>
Mesa 18.2.7 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106577">Bug 106577</a> - broken rendering with nine and nouveau (GM107)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108245">Bug 108245</a> - RADV/Vega: Low mip levels of large BCn textures get corrupted by vkCmdCopyBufferToImage</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108311">Bug 108311</a> - Query buffer object support is broken on r600.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108894">Bug 108894</a> - [anv] vkCmdCopyBuffer() and vkCmdCopyQueryPoolResults() write-after-write hazard</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108909">Bug 108909</a> - Vkd3d test failure test_resolve_non_issued_query_data()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108914">Bug 108914</a> - blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108925">Bug 108925</a> - vkCmdCopyQueryPoolResults(VK_QUERY_RESULT_WAIT_BIT) for timestamps with large query count hangs</li>
</ul>
<h2>Changes</h2>
<p>Alex Smith (1):</p>
<ul>
<li>radv: Flush before vkCmdWriteTimestamp() if needed</li>
</ul>
<p>Bas Nieuwenhuizen (4):</p>
<ul>
<li>radv: Align large buffers to the fragment size.</li>
<li>radv: Clamp gfx9 image view extents to the allocated image extents.</li>
<li>radv/android: Mark android WSI image as shareable.</li>
<li>radv/android: Use buffer metadata to determine scanout compat.</li>
</ul>
<p>Dave Airlie (2):</p>
<ul>
<li>r600: make suballocator 256-bytes align</li>
<li>radv: use 3d shader for gfx9 copies if dst is 3d</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>egl/wayland: bail out when drmGetMagic fails</li>
<li>egl/wayland: plug memory leak in drm_handle_device()</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>v3d: Fix a leak of the transfer helper on screen destroy.</li>
<li>vc4: Fix a leak of the transfer helper on screen destroy.</li>
<li>v3d: Fix a leak of the disassembled instruction string during debug dumps.</li>
</ul>
<p>Eric Engestrom (3):</p>
<ul>
<li>anv: correctly use vulkan 1.0 by default</li>
<li>wsi/display: fix mem leak when freeing swapchains</li>
<li>vulkan/wsi: fix s/,/;/ typo</li>
</ul>
<p>Gurchetan Singh (3):</p>
<ul>
<li>virgl: quadruple command buffer size</li>
<li>virgl: avoid large inline transfers</li>
<li>virgl: don't mark buffers as unclean after a write</li>
</ul>
<p>Juan A. Suarez Romero (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.6</li>
<li>cherry-ignore: freedreno: Fix autotools build.</li>
<li>cherry-ignore: mesa: Revert INTEL_fragment_shader_ordering support</li>
<li>Update version to 18.2.7</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nv50,nvc0: Fix gallium nine regression regarding sampler bindings</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>anv: flush pipeline before query result copies</li>
<li>anv/query: flush render target before copying results</li>
</ul>
<p>Michal Srb (2):</p>
<ul>
<li>gallium: Constify drisw_loader_funcs struct</li>
<li>drisw: Use separate drisw_loader_funcs for shm</li>
</ul>
<p>Nicolai Hähnle (2):</p>
<ul>
<li>egl/wayland: rather obvious build fix</li>
<li>meson: link LLVM 'native' component when LLVM is available</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: rework the TC-compat HTILE hardware bug with COND_EXEC</li>
</ul>
<p>Thomas Hellstrom (2):</p>
<ul>
<li>st/xa: Fix a memory leak</li>
<li>winsys/svga: Fix a memory leak</li>
</ul>
<p>Tobias Klausmann (1):</p>
<ul>
<li>amd/vulkan: meson build - use radv_deps for libvulkan_radeon</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>st/xvmc: Add X11 include path.</li>
</ul>
</div>
</body>
</html>
meson.build
View file @ 419ee200
......@@ -1139,7 +1139,7 @@ endif
llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
llvm_optional_modules = []
if with_amd_vk or with_gallium_radeonsi or with_gallium_r600
llvm_modules += ['amdgpu', 'bitreader', 'ipo']
llvm_modules += ['amdgpu', 'native', 'bitreader', 'ipo']
if with_gallium_r600
llvm_modules += 'asmparser'
endif
......
src/amd/vulkan/meson.build
View file @ 419ee200
......@@ -140,7 +140,7 @@ libvulkan_radeon = shared_library(
],
dependencies : [
dep_llvm, dep_libdrm_amdgpu, dep_thread, dep_elf, dep_dl, dep_m,
dep_valgrind,
dep_valgrind, radv_deps,
idep_nir,
],
c_args : [c_vis_args, no_override_init_args, radv_flags],
......
src/amd/vulkan/radv_android.c
View file @ 419ee200
......@@ -110,17 +110,6 @@ radv_image_from_gralloc(VkDevice device_h,
struct radv_bo *bo = NULL;
VkResult result;
result = radv_image_create(device_h,
&(struct radv_image_create_info) {
.vk_info = base_info,
.scanout = true,
.no_metadata_planes = true},
alloc,
&image_h);
if (result != VK_SUCCESS)
return result;
if (gralloc_info->handle->numFds != 1) {
return vk_errorf(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR,
"VkNativeBufferANDROID::handle::numFds is %d, "
......@@ -133,23 +122,14 @@ radv_image_from_gralloc(VkDevice device_h,
*/
int dma_buf = gralloc_info->handle->data[0];
image = radv_image_from_handle(image_h);
VkDeviceMemory memory_h;
const VkMemoryDedicatedAllocateInfoKHR ded_alloc = {
.sType = VK_STRUCTURE_TYPE_MEMORY_DEDICATED_ALLOCATE_INFO_KHR,
.pNext = NULL,
.buffer = VK_NULL_HANDLE,
.image = image_h
};
const VkImportMemoryFdInfoKHR import_info = {
.sType = VK_STRUCTURE_TYPE_IMPORT_MEMORY_FD_INFO_KHR,
.pNext = &ded_alloc,
.handleType = VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR,
.fd = dup(dma_buf),
};
/* Find the first VRAM memory type, or GART for PRIME images. */
int memory_type_index = -1;
for (int i = 0; i < device->physical_device->memory_properties.memoryTypeCount; ++i) {
......@@ -168,14 +148,49 @@ radv_image_from_gralloc(VkDevice device_h,
&(VkMemoryAllocateInfo) {
.sType = VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO,
.pNext = &import_info,
.allocationSize = image->size,
/* Max buffer size, unused for imports */
.allocationSize = 0x7FFFFFFF,
.memoryTypeIndex = memory_type_index,
},
alloc,
&memory_h);
if (result != VK_SUCCESS)
return result;
struct radeon_bo_metadata md;
device->ws->buffer_get_metadata(radv_device_memory_from_handle(memory_h)->bo, &md);
bool is_scanout;
if (device->physical_device->rad_info.chip_class >= GFX9) {
/* Copied from radeonsi, but is hacky so should be cleaned up. */
is_scanout = md.u.gfx9.swizzle_mode == 0 || md.u.gfx9.swizzle_mode % 4 == 2;
} else {
is_scanout = md.u.legacy.scanout;
}
VkImageCreateInfo updated_base_info = *base_info;
VkExternalMemoryImageCreateInfo external_memory_info = {
.sType = VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_IMAGE_CREATE_INFO,
.pNext = updated_base_info.pNext,
.handleTypes = VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT,
};
updated_base_info.pNext = &external_memory_info;
result = radv_image_create(device_h,
&(struct radv_image_create_info) {
.vk_info = &updated_base_info,
.scanout = is_scanout,
.no_metadata_planes = true},
alloc,
&image_h);
if (result != VK_SUCCESS)
goto fail_create_image;
image = radv_image_from_handle(image_h);
radv_BindImageMemory(device_h, image_h, memory_h, 0);
image->owned_memory = memory_h;
......@@ -185,9 +200,7 @@ radv_image_from_gralloc(VkDevice device_h,
return VK_SUCCESS;
fail_create_image:
fail_size:
radv_DestroyImage(device_h, image_h, alloc);
radv_FreeMemory(device_h, memory_h, alloc);
return result;
}
......
src/amd/vulkan/radv_cmd_buffer.c
View file @ 419ee200
......@@ -1051,7 +1051,7 @@ static void
radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
struct radv_ds_buffer_info *ds,
struct radv_image *image, VkImageLayout layout,
bool requires_cond_write)
bool requires_cond_exec)
{
uint32_t db_z_info = ds->db_z_info;
uint32_t db_z_info_reg;
......@@ -1075,39 +1075,22 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
}
/* When we don't know the last fast clear value we need to emit a
* conditional packet, otherwise we can update DB_Z_INFO directly.
* conditional packet that will eventually skip the following
* SET_CONTEXT_REG packet.
*/
if (requires_cond_write) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
const uint32_t write_space = 0 << 8; /* register */
const uint32_t poll_space = 1 << 4; /* memory */
const uint32_t function = 3 << 0; /* equal to the reference */
const uint32_t options = write_space | poll_space | function;
radeon_emit(cmd_buffer->cs, options);
/* poll address - location of the depth clear value */
if (requires_cond_exec) {
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
/* In presence of stencil format, we have to adjust the base
* address because the first value is the stencil clear value.
*/
if (vk_format_is_stencil(image->vk_format))
va += 4;
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
}
radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
radeon_emit(cmd_buffer->cs, 0u); /* write address high */
radeon_emit(cmd_buffer->cs, db_z_info);
} else {
radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
}
}
static void
radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
......@@ -1253,6 +1236,45 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cs, fui(ds_clear_value.depth));
}
/**
* Update the TC-compat metadata value for this image.
*/
static void
radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
uint32_t value)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, value);
}
static void
radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkClearDepthStencilValue ds_clear_value)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
uint32_t cond_val;
/* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
* depth clear value is 0.0f.
*/
cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
}
/**
* Update the clear depth/stencil values for this image.
*/
......@@ -1266,6 +1288,12 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
if (radv_image_is_tc_compat_htile(image) &&
(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
ds_clear_value);
}
radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
aspects);
}
......@@ -4046,6 +4074,15 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
if (radv_image_is_tc_compat_htile(image)) {
/* Initialize the TC-compat metada value to 0 because by
* default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
* need have to conditionally update its value when performing
* a fast depth clear.
*/
radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
}
}
static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
......
src/amd/vulkan/radv_image.c
View file @ 419ee200
......@@ -853,6 +853,14 @@ radv_image_alloc_htile(struct radv_image *image)
/* + 8 for storing the clear values */
image->clear_value_offset = image->htile_offset + image->surface.htile_size;
image->size = image->clear_value_offset + 8;
if (radv_image_is_tc_compat_htile(image)) {
/* Metadata for the TC-compatible HTILE hardware bug which
* have to be fixed by updating ZRANGE_PRECISION when doing
* fast depth clears to 0.0f.
*/
image->tc_compat_zrange_offset = image->clear_value_offset + 8;
image->size = image->clear_value_offset + 16;
}
image->alignment = align64(image->alignment, image->surface.htile_alignment);
}
......@@ -995,8 +1003,8 @@ radv_image_create(VkDevice _device,
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
radv_image_alloc_htile(image);
image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
radv_image_alloc_htile(image);
} else {
image->surface.htile_size = 0;
}
......@@ -1156,8 +1164,6 @@ radv_image_view_init(struct radv_image_view *iview,
if (device->physical_device->rad_info.chip_class >= GFX9 &&
vk_format_is_compressed(image->vk_format) &&
!vk_format_is_compressed(iview->vk_format)) {
unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
......@@ -1167,8 +1173,8 @@ radv_image_view_init(struct radv_image_view *iview,
lvl_width <<= range->baseMipLevel;
lvl_height <<= range->baseMipLevel;
iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
}
}
......
src/amd/vulkan/radv_meta_bufimage.c
View file @ 419ee200
......@@ -1187,7 +1187,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
src->image->type == VK_IMAGE_TYPE_3D)
(src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D))
pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
......
src/amd/vulkan/radv_private.h
View file @ 419ee200
......@@ -1433,6 +1433,14 @@ struct radv_image {
uint64_t clear_value_offset;
uint64_t dcc_pred_offset;
/*
* Metadata for the TC-compat zrange workaround. If the 32-bit value
* stored at this offset is UINT_MAX, the driver will emit
* DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
* SET_CONTEXT_REG packet.
*/
uint64_t tc_compat_zrange_offset;
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
};
......
src/amd/vulkan/radv_query.c
View file @ 419ee200
......@@ -1085,6 +1085,22 @@ void radv_CmdResetQueryPool(
}
}
static void emit_query_flush(struct radv_cmd_buffer *cmd_buffer,
struct radv_query_pool *pool)
{
if (cmd_buffer->pending_reset_query) {
if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
/* Only need to flush caches if the query pool size is
* large enough to be resetted using the compute shader
* path. Small pools don't need any cache flushes
* because we use a CP dma clear.
*/
si_emit_cache_flush(cmd_buffer);
cmd_buffer->pending_reset_query = false;
}
}
}
static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
uint64_t va,
VkQueryType query_type,
......@@ -1209,17 +1225,7 @@ void radv_CmdBeginQuery(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
if (cmd_buffer->pending_reset_query) {
if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
/* Only need to flush caches if the query pool size is
* large enough to be resetted using the compute shader
* path. Small pools don't need any cache flushes
* because we use a CP dma clear.
*/
si_emit_cache_flush(cmd_buffer);
cmd_buffer->pending_reset_query = false;
}
}
emit_query_flush(cmd_buffer, pool);
va += pool->stride * query;
......@@ -1280,6 +1286,8 @@ void radv_CmdWriteTimestamp(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
emit_query_flush(cmd_buffer, pool);
int num_queries = 1;
if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
......
src/amd/vulkan/radv_radeon_winsys.h
View file @ 419ee200
......@@ -223,6 +223,8 @@ struct radeon_winsys {
void (*buffer_set_metadata)(struct radeon_winsys_bo *bo,
struct radeon_bo_metadata *md);
void (*buffer_get_metadata)(struct radeon_winsys_bo *bo,
struct radeon_bo_metadata *md);
void (*buffer_virtual_bind)(struct radeon_winsys_bo *parent,
uint64_t offset, uint64_t size,
......
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
View file @ 419ee200
......@@ -304,8 +304,12 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
return NULL;
}
unsigned virt_alignment = alignment;
if (size >= ws->info.pte_fragment_size)
virt_alignment = MAX2(virt_alignment, ws->info.pte_fragment_size);
r = amdgpu_va_range_alloc(ws->dev, amdgpu_gpu_va_range_general,
size, alignment, 0, &va, &va_handle,
size, virt_alignment, 0, &va, &va_handle,
(flags & RADEON_FLAG_32BIT ? AMDGPU_VA_RANGE_32_BIT : 0) |
AMDGPU_VA_RANGE_HIGH);
if (r)
......@@ -536,6 +540,21 @@ radv_amdgpu_winsys_get_fd(struct radeon_winsys *_ws,
return true;
}
static unsigned eg_tile_split(unsigned tile_split)
{
switch (tile_split) {
case 0: tile_split = 64; break;
case 1: tile_split = 128; break;
case 2: tile_split = 256; break;
case 3: tile_split = 512; break;
default:
case 4: tile_split = 1024; break;
case 5: tile_split = 2048; break;
case 6: tile_split = 4096; break;
}
return tile_split;
}
static unsigned radv_eg_tile_split_rev(unsigned eg_tile_split)
{
switch (eg_tile_split) {
......@@ -589,6 +608,43 @@ radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys_bo *_bo,
amdgpu_bo_set_metadata(bo->bo, &metadata);
}
static void
radv_amdgpu_winsys_bo_get_metadata(struct radeon_winsys_bo *_bo,
struct radeon_bo_metadata *md)
{
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
struct amdgpu_bo_info info = {0};
int r = amdgpu_bo_query_info(bo->bo, &info);
if (r)
return;
uint64_t tiling_flags = info.metadata.tiling_info;
if (bo->ws->info.chip_class >= GFX9) {
md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
} else {
md->u.legacy.microtile = RADEON_LAYOUT_LINEAR;
md->u.legacy.macrotile = RADEON_LAYOUT_LINEAR;
if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
md->u.legacy.macrotile = RADEON_LAYOUT_TILED;
else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
md->u.legacy.microtile = RADEON_LAYOUT_TILED;
md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
md->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
md->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
md->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
md->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
md->u.legacy.scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */
}
md->size_metadata = info.metadata.size_metadata;
memcpy(md->metadata, info.metadata.umd_metadata, sizeof(md->metadata));
}
void radv_amdgpu_bo_init_functions(struct radv_amdgpu_winsys *ws)
{
ws->base.buffer_create = radv_amdgpu_winsys_bo_create;
......@@ -599,5 +655,6 @@ void radv_amdgpu_bo_init_functions(struct radv_amdgpu_winsys *ws)
ws->base.buffer_from_fd = radv_amdgpu_winsys_bo_from_fd;
ws->base.buffer_get_fd = radv_amdgpu_winsys_get_fd;
ws->base.buffer_set_metadata = radv_amdgpu_winsys_bo_set_metadata;
ws->base.buffer_get_metadata = radv_amdgpu_winsys_bo_get_metadata;
ws->base.buffer_virtual_bind = radv_amdgpu_winsys_bo_virtual_bind;
}
src/broadcom/compiler/vir_to_qpu.c
View file @ 419ee200
......@@ -364,6 +364,7 @@ v3d_dump_qpu(struct v3d_compile *c)
for (int i = 0; i < c->qpu_inst_count; i++) {
const char *str = v3d_qpu_disasm(c->devinfo, c->qpu_insts[i]);
fprintf(stderr, "0x%016"PRIx64" %s\n", c->qpu_insts[i], str);
ralloc_free((void *)str);
}
fprintf(stderr, "\n");
}
......
src/egl/drivers/dri2/platform_wayland.c
View file @ 419ee200
......@@ -1128,13 +1128,22 @@ drm_handle_device(void *data, struct wl_drm *drm, const char *device)
if (dri2_dpy->fd == -1) {
_eglLog(_EGL_WARNING, "wayland-egl: could not open %s (%s)",
dri2_dpy->device_name, strerror(errno));
free(dri2_dpy->device_name);
dri2_dpy->device_name = NULL;
return;
}
if (drmGetNodeTypeFromFd(dri2_dpy->fd) == DRM_NODE_RENDER) {
dri2_dpy->authenticated = true;
} else {
drmGetMagic(dri2_dpy->fd, &magic);
if (drmGetMagic(dri2_dpy->fd, &magic)) {
close(dri2_dpy->fd);
dri2_dpy->fd = -1;
free(dri2_dpy->device_name);
dri2_dpy->device_name = NULL;
_eglLog(_EGL_WARNING, "wayland-egl: drmGetMagic failed");
return;
}
wl_drm_authenticate(dri2_dpy->wl_drm, magic);
}
}
......
src/gallium/auxiliary/pipe-loader/pipe_loader.h
View file @ 419ee200
......@@ -139,7 +139,7 @@ pipe_loader_release(struct pipe_loader_device **devs, int ndev);
*/
bool
pipe_loader_sw_probe_dri(struct pipe_loader_device **devs,
struct drisw_loader_funcs *drisw_lf);
const struct drisw_loader_funcs *drisw_lf);
/**
* Initialize a kms backed sw device given an fd.
......
src/gallium/auxiliary/pipe-loader/pipe_loader_sw.c
View file @ 419ee200
......@@ -128,7 +128,7 @@ pipe_loader_sw_probe_teardown_common(struct pipe_loader_sw_device *sdev)
#ifdef HAVE_PIPE_LOADER_DRI
bool
pipe_loader_sw_probe_dri(struct pipe_loader_device **devs, struct drisw_loader_funcs *drisw_lf)
pipe_loader_sw_probe_dri(struct pipe_loader_device **devs, const struct drisw_loader_funcs *drisw_lf)
{
struct pipe_loader_sw_device *sdev = CALLOC_STRUCT(pipe_loader_sw_device);
int i;
......
src/gallium/drivers/nouveau/nv50/nv50_state.c
View file @ 419ee200
......@@ -600,25 +600,23 @@ static inline void
nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
unsigned nr, void **hwcso)
{
unsigned highest_found = 0;
unsigned i;
assert(nr <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nr; ++i) {
struct nv50_tsc_entry *old = nv50->samplers[s][i];
if (hwcso[i])
highest_found = i;
nv50->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
if (old)
nv50_screen_tsc_unlock(nv50->screen, old);
}
assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
for (; i < nv50->num_samplers[s]; ++i) {
if (nv50->samplers[s][i]) {
nv50_screen_tsc_unlock(nv50->screen, nv50->samplers[s][i]);
nv50->samplers[s][i] = NULL;
}
}
nv50->num_samplers[s] = nr;
if (nr >= nv50->num_samplers[s])
nv50->num_samplers[s] = highest_found + 1;
nv50->dirty_3d |= NV50_NEW_3D_SAMPLERS;
}
......
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
View file @ 419ee200
......@@ -464,11 +464,15 @@ nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
unsigned s,
unsigned nr, void **hwcso)
{
unsigned highest_found = 0;
unsigned i;
for (i = 0; i < nr; ++i) {
struct nv50_tsc_entry *old = nvc0->samplers[s][i];
if (hwcso[i])
highest_found = i;
if (hwcso[i] == old)
continue;
nvc0->samplers_dirty[s] |= 1 << i;
......@@ -477,14 +481,8 @@ nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
if (old)
nvc0_screen_tsc_unlock(nvc0->screen, old);
}
for (; i < nvc0->num_samplers[s]; ++i) {
if (nvc0->samplers[s][i]) {
nvc0_screen_tsc_unlock(nvc0->screen, nvc0->samplers[s][i]);
nvc0->samplers[s][i] = NULL;
}
}
nvc0->num_samplers[s] = nr;
if (nr >= nvc0->num_samplers[s])
nvc0->num_samplers[s] = highest_found + 1;
}
static void
......