.travis.yml

@@ -53,10 +53,10 @@ install:
 script:
   - if test "x$BUILD" = xmeson; then
       meson _build -Dbuild-tests=true;
-      ninja -C _build;
-      ninja -C _build test;
+      ninja -C _build || travis_terminate 1;
+      ninja -C _build test || travis_terminate 1;
     fi
   - if test "x$BUILD" = xscons; then
-      scons;
-      scons check;
+      scons || travis_terminate 1;
+      scons check || travis_terminate 1;
     fi

VERSION

-19.2.0-rc2
+19.2.0-rc3

debian/changelog

-mesa (19.2.0~rc2-2) UNRELEASED; urgency=medium
+mesa (19.2.0~rc3-1) experimental; urgency=medium
 
+  * New upstream release candidate.
   * control,rules: Restore libva-dev build-dep and nolibva build
     profile.
 
- -- Timo Aaltonen <tjaalton@debian.org>  Tue, 10 Sep 2019 14:50:21 +0300
+ -- Timo Aaltonen <tjaalton@debian.org>  Thu, 12 Sep 2019 15:34:19 +0300
 
 mesa (19.2.0~rc2-1) experimental; urgency=medium
 

src/amd/common/ac_gpu_info.h

@@ -173,7 +173,7 @@ unsigned ac_get_compute_resource_limits(struct radeon_info *info,
 					unsigned max_waves_per_sh,
 					unsigned threadgroups_per_cu);
 
-static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
+static inline unsigned ac_get_max_wave64_per_simd(enum radeon_family family)
 {
 
 	switch (family) {
@@ -188,10 +188,26 @@ static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
 	}
 }
 
+static inline unsigned ac_get_num_physical_vgprs(enum chip_class chip_class,
+						 unsigned wave_size)
+{
+	/* The number is per SIMD. */
+	if (chip_class >= GFX10)
+		return wave_size == 32 ? 1024 : 512;
+	else
+		return 256;
+}
+
 static inline uint32_t
-ac_get_num_physical_sgprs(enum chip_class chip_class)
+ac_get_num_physical_sgprs(const struct radeon_info *info)
 {
-	return chip_class >= GFX8 ? 800 : 512;
+	/* The number is per SIMD. There is enough SGPRs for the maximum number
+	 * of Wave32, which is double the number for Wave64.
+	 */
+	if (info->chip_class >= GFX10)
+		return 128 * ac_get_max_wave64_per_simd(info->family) * 2;
+
+	return info->chip_class >= GFX8 ? 800 : 512;
 }
 
 #ifdef __cplusplus

src/amd/common/ac_nir_to_llvm.c

@@ -42,8 +42,6 @@ struct ac_nir_context {
 
 	LLVMValueRef *ssa_defs;
 
-	LLVMValueRef scratch;
-
 	struct hash_table *defs;
 	struct hash_table *phis;
 	struct hash_table *vars;
@@ -3618,50 +3616,6 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
 	case nir_intrinsic_mbcnt_amd:
 		result = ac_build_mbcnt(&ctx->ac, get_src(ctx, instr->src[0]));
 		break;
-	case nir_intrinsic_load_scratch: {
-		LLVMValueRef offset = get_src(ctx, instr->src[0]);
-		LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->scratch,
-						 offset);
-		LLVMTypeRef comp_type =
-			LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size);
-		LLVMTypeRef vec_type =
-			instr->dest.ssa.num_components == 1 ? comp_type :
-			LLVMVectorType(comp_type, instr->dest.ssa.num_components);
-		unsigned addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
-		ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
-				       LLVMPointerType(vec_type, addr_space), "");
-		result = LLVMBuildLoad(ctx->ac.builder, ptr, "");
-		break;
-	}
-	case nir_intrinsic_store_scratch: {
-		LLVMValueRef offset = get_src(ctx, instr->src[1]);
-		LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->scratch,
-						 offset);
-		LLVMTypeRef comp_type =
-			LLVMIntTypeInContext(ctx->ac.context, instr->src[0].ssa->bit_size);
-		unsigned addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
-		ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
-				       LLVMPointerType(comp_type, addr_space), "");
-		LLVMValueRef src = get_src(ctx, instr->src[0]);
-		unsigned wrmask = nir_intrinsic_write_mask(instr);
-		while (wrmask) {
-			int start, count;
-			u_bit_scan_consecutive_range(&wrmask, &start, &count);
-			
-			LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, start, false);
-			LLVMValueRef offset_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &offset, 1, "");
-			LLVMTypeRef vec_type =
-				count == 1 ? comp_type : LLVMVectorType(comp_type, count);
-			offset_ptr = LLVMBuildBitCast(ctx->ac.builder,
-						      offset_ptr,
-						      LLVMPointerType(vec_type, addr_space),
-						      "");
-			LLVMValueRef offset_src =
-				ac_extract_components(&ctx->ac, src, start, count);
-			LLVMBuildStore(ctx->ac.builder, offset_src, offset_ptr);
-		}
-		break;
-	}
 	default:
 		fprintf(stderr, "Unknown intrinsic: ");
 		nir_print_instr(&instr->instr, stderr);
@@ -4562,18 +4516,6 @@ setup_locals(struct ac_nir_context *ctx,
 	}
 }
 
-static void
-setup_scratch(struct ac_nir_context *ctx,
-	      struct nir_shader *shader)
-{
-	if (shader->scratch_size == 0)
-		return;
-
-	ctx->scratch = ac_build_alloca_undef(&ctx->ac,
-					     LLVMArrayType(ctx->ac.i8, shader->scratch_size),
-					     "scratch");
-}
-
 static void
 setup_shared(struct ac_nir_context *ctx,
 	     struct nir_shader *nir)
@@ -4619,7 +4561,6 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 	ctx.ssa_defs = calloc(func->impl->ssa_alloc, sizeof(LLVMValueRef));
 
 	setup_locals(&ctx, func);
-	setup_scratch(&ctx, nir);
 
 	if (gl_shader_stage_is_compute(nir->info.stage))
 		setup_shared(&ctx, nir);
@@ -4641,15 +4582,6 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct ac_shader_abi *abi,
 void
 ac_lower_indirect_derefs(struct nir_shader *nir, enum chip_class chip_class)
 {
-	/* Lower large variables to scratch first so that we won't bloat the
-	 * shader by generating large if ladders for them. We later lower
-	 * scratch to alloca's, assuming LLVM won't generate VGPR indexing.
-	 */
-	NIR_PASS_V(nir, nir_lower_vars_to_scratch,
-		   nir_var_function_temp,
-		   256,
-		   glsl_get_natural_size_align_bytes);
-
 	/* While it would be nice not to have this flag, we are constrained
 	 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
 	 */

src/amd/vulkan/radv_device.c

@@ -589,8 +589,9 @@ static int radv_get_instance_extension_index(const char *name)
 
 static const char radv_dri_options_xml[] =
 DRI_CONF_BEGIN
-	DRI_CONF_SECTION_QUALITY
+	DRI_CONF_SECTION_PERFORMANCE
 		DRI_CONF_ADAPTIVE_SYNC("true")
+		DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
 	DRI_CONF_SECTION_END
 DRI_CONF_END;
 
@@ -1306,7 +1307,7 @@ void radv_GetPhysicalDeviceProperties2(
 
 			/* SGPR. */
 			properties->sgprsPerSimd =
-				ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
+				ac_get_num_physical_sgprs(&pdevice->rad_info);
 			properties->minSgprAllocation =
 				pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
 			properties->maxSgprAllocation =

src/amd/vulkan/radv_shader.c

@@ -389,6 +389,8 @@ radv_shader_compile_to_nir(struct radv_device *device,
 		NIR_PASS_V(nir, nir_remove_dead_variables,
 		           nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
 
+		NIR_PASS_V(nir, nir_propagate_invariant);
+
 		NIR_PASS_V(nir, nir_lower_system_values);
 		NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
 		NIR_PASS_V(nir, radv_nir_lower_ycbcr_textures, layout);
@@ -1341,7 +1343,7 @@ radv_get_max_waves(struct radv_device *device,
 	unsigned max_simd_waves;
 	unsigned lds_per_wave = 0;
 
-	max_simd_waves = ac_get_max_simd_waves(device->physical_device->rad_info.family);
+	max_simd_waves = ac_get_max_wave64_per_simd(device->physical_device->rad_info.family);
 
 	if (stage == MESA_SHADER_FRAGMENT) {
 		lds_per_wave = conf->lds_size * lds_increment +
@@ -1357,7 +1359,8 @@ radv_get_max_waves(struct radv_device *device,
 	if (conf->num_sgprs)
 		max_simd_waves =
 			MIN2(max_simd_waves,
-			     ac_get_num_physical_sgprs(chip_class) / conf->num_sgprs);
+			     ac_get_num_physical_sgprs(&device->physical_device->rad_info) /
+			     conf->num_sgprs);
 
 	if (conf->num_vgprs)
 		max_simd_waves =
@@ -1454,7 +1457,7 @@ radv_GetShaderInfoAMD(VkDevice _device,
 			VkShaderStatisticsInfoAMD statistics = {};
 			statistics.shaderStageMask = shaderStage;
 			statistics.numPhysicalVgprs = RADV_NUM_PHYSICAL_VGPRS;
-			statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(device->physical_device->rad_info.chip_class);
+			statistics.numPhysicalSgprs = ac_get_num_physical_sgprs(&device->physical_device->rad_info);
 			statistics.numAvailableSgprs = statistics.numPhysicalSgprs;
 
 			if (stage == MESA_SHADER_COMPUTE) {

src/compiler/nir/nir.h

@@ -3378,6 +3378,7 @@ void nir_calc_dominance(nir_shader *shader);
 
 nir_block *nir_dominance_lca(nir_block *b1, nir_block *b2);
 bool nir_block_dominates(nir_block *parent, nir_block *child);
+bool nir_block_is_unreachable(nir_block *block);
 
 void nir_dump_dom_tree_impl(nir_function_impl *impl, FILE *fp);
 void nir_dump_dom_tree(nir_shader *shader, FILE *fp);

src/compiler/nir/nir_dominance.c

@@ -239,6 +239,20 @@ nir_block_dominates(nir_block *parent, nir_block *child)
           child->dom_post_index <= parent->dom_post_index;
 }
 
+bool
+nir_block_is_unreachable(nir_block *block)
+{
+   assert(nir_cf_node_get_function(&block->cf_node)->valid_metadata &
+          nir_metadata_dominance);
+   assert(nir_cf_node_get_function(&block->cf_node)->valid_metadata &
+          nir_metadata_block_index);
+
+   /* Unreachable blocks have no dominator.  The only reachable block with no
+    * dominator is the start block which has index 0.
+    */
+   return block->index > 0 && block->imm_dom == NULL;
+}
+
 void
 nir_dump_dom_tree_impl(nir_function_impl *impl, FILE *fp)
 {

src/compiler/nir/nir_from_ssa.c

@@ -827,7 +827,7 @@ nir_convert_from_ssa(nir_shader *shader, bool phi_webs_only)
 
 static void
 place_phi_read(nir_shader *shader, nir_register *reg,
-               nir_ssa_def *def, nir_block *block)
+               nir_ssa_def *def, nir_block *block, unsigned depth)
 {
    if (block != def->parent_instr->block) {
       /* Try to go up the single-successor tree */
@@ -840,14 +840,24 @@ place_phi_read(nir_shader *shader, nir_register *reg,
          }
       }
 
-      if (all_single_successors) {
+      if (all_single_successors && depth < 32) {
          /* All predecessors of this block have exactly one successor and it
           * is this block so they must eventually lead here without
           * intersecting each other.  Place the reads in the predecessors
           * instead of this block.
+          *
+          * We only let this function recurse 32 times because it can recurse
+          * indefinitely in the presence of infinite loops.  Because we're
+          * crawling a single-successor chain, it doesn't matter where we
+          * place it so it's ok to stop at an arbitrary distance.
+          *
+          * TODO: One day, we could detect back edges and avoid the recursion
+          * that way.
           */
-         set_foreach(block->predecessors, entry)
-            place_phi_read(shader, reg, def, (nir_block *)entry->key);
+         set_foreach(block->predecessors, entry) {
+            place_phi_read(shader, reg, def, (nir_block *)entry->key,
+                           depth + 1);
+         }
          return;
       }
    }
@@ -902,7 +912,7 @@ nir_lower_phis_to_regs_block(nir_block *block)
 
       nir_foreach_phi_src(src, phi) {
          assert(src->src.is_ssa);
-         place_phi_read(shader, reg, src->src.ssa, src->pred);
+         place_phi_read(shader, reg, src->src.ssa, src->pred, 0);
       }
 
       nir_instr_remove(&phi->instr);

src/compiler/nir/nir_lower_io.c

@@ -879,39 +879,49 @@ build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin,
    if (mode != nir_var_mem_ubo && mode != nir_var_shader_in && mode != nir_var_mem_shared)
       nir_intrinsic_set_access(load, nir_intrinsic_access(intrin));
 
+   unsigned bit_size = intrin->dest.ssa.bit_size;
+   if (bit_size == 1) {
+      /* TODO: Make the native bool bit_size an option. */
+      bit_size = 32;
+   }
+
    /* TODO: We should try and provide a better alignment.  For OpenCL, we need
     * to plumb the alignment through from SPIR-V when we have one.
     */
-   nir_intrinsic_set_align(load, intrin->dest.ssa.bit_size / 8, 0);
+   nir_intrinsic_set_align(load, bit_size / 8, 0);
 
    assert(intrin->dest.is_ssa);
    load->num_components = num_components;
    nir_ssa_dest_init(&load->instr, &load->dest, num_components,
-                     intrin->dest.ssa.bit_size, intrin->dest.ssa.name);
+                     bit_size, intrin->dest.ssa.name);
 
-   assert(load->dest.ssa.bit_size % 8 == 0);
+   assert(bit_size % 8 == 0);
 
+   nir_ssa_def *result;
    if (addr_format_needs_bounds_check(addr_format)) {
       /* The Vulkan spec for robustBufferAccess gives us quite a few options
        * as to what we can do with an OOB read.  Unfortunately, returning
        * undefined values isn't one of them so we return an actual zero.
        */
-      nir_ssa_def *zero = nir_imm_zero(b, load->num_components,
-                                          load->dest.ssa.bit_size);
+      nir_ssa_def *zero = nir_imm_zero(b, load->num_components, bit_size);
 
-      const unsigned load_size =
-         (load->dest.ssa.bit_size / 8) * load->num_components;
+      const unsigned load_size = (bit_size / 8) * load->num_components;
       nir_push_if(b, addr_is_in_bounds(b, addr, addr_format, load_size));
 
       nir_builder_instr_insert(b, &load->instr);
 
       nir_pop_if(b, NULL);
 
-      return nir_if_phi(b, &load->dest.ssa, zero);
+      result = nir_if_phi(b, &load->dest.ssa, zero);
    } else {
       nir_builder_instr_insert(b, &load->instr);
-      return &load->dest.ssa;
+      result = &load->dest.ssa;
    }
+
+   if (intrin->dest.ssa.bit_size == 1)
+      result = nir_i2b(b, result);
+
+   return result;
 }
 
 static void
@@ -943,6 +953,11 @@ build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin,
 
    nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, op);
 
+   if (value->bit_size == 1) {
+      /* TODO: Make the native bool bit_size an option. */
+      value = nir_b2i(b, value, 32);
+   }
+
    store->src[0] = nir_src_for_ssa(value);
    if (addr_format_is_global(addr_format)) {
       store->src[1] = nir_src_for_ssa(addr_to_global(b, addr, addr_format));

src/compiler/nir/nir_opt_comparison_pre.c

@@ -107,8 +107,10 @@ push_block(struct block_queue *bq)
 
    if (!u_vector_init(&bi->instructions,
                       sizeof(nir_alu_instr *),
-                      8 * sizeof(nir_alu_instr *)))
+                      8 * sizeof(nir_alu_instr *))) {
+      free(bi);
       return NULL;
+   }
 
    exec_list_push_tail(&bq->blocks, &bi->node);
 

src/compiler/nir/nir_opt_dead_cf.c

@@ -355,6 +355,17 @@ opt_dead_cf_impl(nir_function_impl *impl)
 
    if (progress) {
       nir_metadata_preserve(impl, nir_metadata_none);
+
+      /* The CF manipulation code called by this pass is smart enough to keep
+       * from breaking any SSA use/def chains by replacing any uses of removed
+       * instructions with SSA undefs.  However, it's not quite smart enough
+       * to always preserve the dominance properties.  In particular, if you
+       * remove the one break from a loop, stuff in the loop may still be used
+       * outside the loop even though there's no path between the two.  We can
+       * easily fix these issues by calling nir_repair_ssa which will ensure
+       * that the dominance properties hold.
+       */
+      nir_repair_ssa_impl(impl);
    } else {
 #ifndef NDEBUG
       impl->valid_metadata &= ~nir_metadata_not_properly_reset;

src/compiler/nir/nir_range_analysis.c

@@ -31,6 +31,12 @@
  * the result.
  */
 
+static bool
+is_not_negative(enum ssa_ranges r)
+{
+   return r == gt_zero || r == ge_zero || r == eq_zero;
+}
+
 static void *
 pack_data(const struct ssa_result_range r)
 {
@@ -457,6 +463,7 @@ analyze_expression(const nir_alu_instr *instr, unsigned src,
 
       r = analyze_expression(alu, 0, ht);
 
+      r.is_integral = r.is_integral && is_not_negative(r.range);
       r.range = table[r.range];
       break;
    }

src/compiler/nir/nir_repair_ssa.c

@@ -71,7 +71,8 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
 
    bool is_valid = true;
    nir_foreach_use(src, def) {
-      if (!nir_block_dominates(def->parent_instr->block, get_src_block(src))) {
+      if (nir_block_is_unreachable(get_src_block(src)) ||
+          !nir_block_dominates(def->parent_instr->block, get_src_block(src))) {
          is_valid = false;
          break;
       }
@@ -80,7 +81,8 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
    nir_foreach_if_use(src, def) {
       nir_block *block_before_if =
          nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
-      if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
+      if (nir_block_is_unreachable(block_before_if) ||
+          !nir_block_dominates(def->parent_instr->block, block_before_if)) {
          is_valid = false;
          break;
       }
@@ -101,16 +103,45 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
 
    nir_foreach_use_safe(src, def) {
       nir_block *src_block = get_src_block(src);
-      if (!nir_block_dominates(def->parent_instr->block, src_block)) {
-         nir_instr_rewrite_src(src->parent_instr, src, nir_src_for_ssa(
-            nir_phi_builder_value_get_block_def(val, src_block)));
+      if (nir_block_is_unreachable(src_block) ||
+          !nir_block_dominates(def->parent_instr->block, src_block)) {
+         nir_ssa_def *block_def =
+            nir_phi_builder_value_get_block_def(val, src_block);
+
+         /* If def was a deref and the use we're looking at is a deref that
+          * isn't a cast, we need to wrap it in a cast so we don't loose any
+          * deref information.
+          */
+         if (def->parent_instr->type == nir_instr_type_deref &&
+             src->parent_instr->type == nir_instr_type_deref &&
+             nir_instr_as_deref(src->parent_instr)->deref_type != nir_deref_type_cast) {
+            nir_deref_instr *cast =
+               nir_deref_instr_create(state->impl->function->shader,
+                                      nir_deref_type_cast);
+
+            nir_deref_instr *deref = nir_instr_as_deref(def->parent_instr);
+            cast->mode = deref->mode;
+            cast->type = deref->type;
+            cast->parent = nir_src_for_ssa(block_def);
+            cast->cast.ptr_stride = nir_deref_instr_ptr_as_array_stride(deref);
+
+            nir_ssa_dest_init(&cast->instr, &cast->dest,
+                              def->num_components, def->bit_size, NULL);
+            nir_instr_insert(nir_before_instr(src->parent_instr),
+                             &cast->instr);
+            block_def = &cast->dest.ssa;
+         }
+
+         nir_instr_rewrite_src(src->parent_instr, src,
+                               nir_src_for_ssa(block_def));
       }
    }
 
    nir_foreach_if_use_safe(src, def) {
       nir_block *block_before_if =
          nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
-      if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
+      if (nir_block_is_unreachable(block_before_if) ||
+          !nir_block_dominates(def->parent_instr->block, block_before_if)) {
          nir_if_rewrite_condition(src->parent_if, nir_src_for_ssa(
             nir_phi_builder_value_get_block_def(val, block_before_if)));
       }

src/compiler/nir/nir_split_vars.c

@@ -427,8 +427,11 @@ get_array_deref_info(nir_deref_instr *deref,
    if (!(deref->mode & modes))
       return NULL;
 
-   return get_array_var_info(nir_deref_instr_get_variable(deref),
-                             var_info_map);
+   nir_variable *var = nir_deref_instr_get_variable(deref);
+   if (var == NULL)
+      return NULL;
+
+   return get_array_var_info(var, var_info_map);
 }
 
 static void

src/egl/main/egldisplay.c

@@ -38,6 +38,7 @@
 #include <unistd.h>
 #include <fcntl.h>
 #include "c11/threads.h"
+#include "util/macros.h"
 #include "util/u_atomic.h"
 
 #include "eglcontext.h"
@@ -66,13 +67,14 @@
 static const struct {
    _EGLPlatformType platform;
    const char *name;
-} egl_platforms[_EGL_NUM_PLATFORMS] = {
+} egl_platforms[] = {
    { _EGL_PLATFORM_X11, "x11" },
    { _EGL_PLATFORM_WAYLAND, "wayland" },
    { _EGL_PLATFORM_DRM, "drm" },
    { _EGL_PLATFORM_ANDROID, "android" },
    { _EGL_PLATFORM_HAIKU, "haiku" },
    { _EGL_PLATFORM_SURFACELESS, "surfaceless" },
+   { _EGL_PLATFORM_DEVICE, "device" },
 };
 
 
@@ -86,6 +88,9 @@ _eglGetNativePlatformFromEnv(void)
    const char *plat_name;
    EGLint i;
 
+   static_assert(ARRAY_SIZE(egl_platforms) == _EGL_NUM_PLATFORMS,
+                 "Missing platform");
+
    plat_name = getenv("EGL_PLATFORM");
    /* try deprecated env variable */
    if (!plat_name || !plat_name[0])
@@ -93,7 +98,7 @@ _eglGetNativePlatformFromEnv(void)
    if (!plat_name || !plat_name[0])
       return _EGL_INVALID_PLATFORM;
 
-   for (i = 0; i < _EGL_NUM_PLATFORMS; i++) {
+   for (i = 0; i < ARRAY_SIZE(egl_platforms); i++) {
       if (strcmp(egl_platforms[i].name, plat_name) == 0) {
          plat = egl_platforms[i].platform;
          break;

src/egl/main/egldriver.c

@@ -56,8 +56,10 @@ _eglGetDriver(void)
 
    if (!_eglDriver) {
       _eglDriver = calloc(1, sizeof(*_eglDriver));
-      if (!_eglDriver)
+      if (!_eglDriver) {
+         mtx_unlock(&_eglModuleMutex);
          return NULL;
+      }
       _eglInitDriver(_eglDriver);
    }
 

src/freedreno/drm-shim/freedreno_noop.c

@@ -84,14 +84,15 @@ msm_ioctl_gem_info(int fd, unsigned long request, void *arg)
 	switch (args->info) {
 	case MSM_INFO_GET_OFFSET:
 		args->value = drm_shim_bo_get_mmap_offset(shim_fd, bo);
-		return 0;
+		break;
 	case MSM_INFO_GET_IOVA:
 		args->value = msm_bo(bo)->offset;
-		return 0;
+		break;
 	case MSM_INFO_SET_NAME:
-		return 0;
+		break;
 	default:
 		fprintf(stderr, "Unknown DRM_IOCTL_MSM_GEM_INFO %d\n", args->info);
+		drm_shim_bo_put(bo);
 		return -1;
 	}
 

src/gallium/auxiliary/indices/u_indices_gen.py

@@ -211,15 +211,15 @@ def postamble():
 
 def points(intype, outtype, inpv, outpv, pr):
     preamble(intype, outtype, inpv, outpv, pr, prim='points')
-    print('  for (i = start; i < (out_nr+start); i++) { ')
-    do_point( intype, outtype, 'out+i',  'i' );
+    print('  for (i = start, j = 0; j < out_nr; j++, i++) { ')
+    do_point( intype, outtype, 'out+j',  'i' );
     print('   }')
     postamble()
 
 def lines(intype, outtype, inpv, outpv, pr):
     preamble(intype, outtype, inpv, outpv, pr, prim='lines')
-    print('  for (i = start; i < (out_nr+start); i+=2) { ')
-    do_line( intype, outtype, 'out+i',  'i', 'i+1', inpv, outpv );
+    print('  for (i = start, j = 0; j < out_nr; j+=2, i+=2) { ')
+    do_line( intype, outtype, 'out+j',  'i', 'i+1', inpv, outpv );
     print('   }')
     postamble()
 
@@ -240,8 +240,8 @@ def lineloop(intype, outtype, inpv, outpv, pr):
 
 def tris(intype, outtype, inpv, outpv, pr):
     preamble(intype, outtype, inpv, outpv, pr, prim='tris')
-    print('  for (i = start; i < (out_nr+start); i+=3) { ')
-    do_tri( intype, outtype, 'out+i',  'i', 'i+1', 'i+2', inpv, outpv );
+    print('  for (i = start, j = 0; j < out_nr; j+=3, i+=3) { ')
+    do_tri( intype, outtype, 'out+j',  'i', 'i+1', 'i+2', inpv, outpv );
     print('   }')
     postamble()
 
@@ -377,8 +377,8 @@ def quadstrip(intype, outtype, inpv, outpv, pr):
 
 def linesadj(intype, outtype, inpv, outpv, pr):
     preamble(intype, outtype, inpv, outpv, pr, prim='linesadj')
-    print('  for (i = start; i < (out_nr+start); i+=4) { ')
-    do_lineadj( intype, outtype, 'out+i',  'i+0', 'i+1', 'i+2', 'i+3', inpv, outpv )
+    print('  for (i = start, j = 0; j < out_nr; j+=4, i+=4) { ')
+    do_lineadj( intype, outtype, 'out+j',  'i+0', 'i+1', 'i+2', 'i+3', inpv, outpv )
     print('  }')
     postamble()
 
@@ -393,8 +393,8 @@ def linestripadj(intype, outtype, inpv, outpv, pr):
 
 def trisadj(intype, outtype, inpv, outpv, pr):
     preamble(intype, outtype, inpv, outpv, pr, prim='trisadj')
-    print('  for (i = start; i < (out_nr+start); i+=6) { ')
-    do_triadj( intype, outtype, 'out+i',  'i+0', 'i+1', 'i+2', 'i+3',
+    print('  for (i = start, j = 0; j < out_nr; j+=6, i+=6) { ')
+    do_triadj( intype, outtype, 'out+j',  'i+0', 'i+1', 'i+2', 'i+3',
                'i+4', 'i+5', inpv, outpv )
     print('  }')
     postamble()