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debian/changelog
View file @ 732a10e3
mesa (19.1.4-1) unstable; urgency=medium
* New upstream release. (Closes: #933753, #933906)
-- Timo Aaltonen <tjaalton@debian.org> Thu, 08 Aug 2019 07:30:48 +0300
mesa (19.1.2-1) unstable; urgency=medium
* New upstream bugfix release.
......
docs/relnotes/19.1.2.html
View file @ 732a10e3
......@@ -30,7 +30,7 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
813a144ea8ebefb7b48b6733f3f603855b0f61268d86cc1cc26a6b4be908fcfd mesa-19.1.2.tar.xz
</pre>
......
docs/relnotes/19.1.3.html 0 → 100644
View file @ 732a10e3
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.1.3 Release Notes / July 23, 2019</h1>
<p>
Mesa 19.1.3 is a bug fix release which fixes bugs found since the 19.1.2 release.
</p>
<p>
Mesa 19.1.3 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
845460b2225d15c15d4a9743dec798ff0b7396b533011d43e774e67f7825b7e0 mesa-19.1.3.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109203">Bug 109203</a> - [cfl dxvk] GPU Crash Launching Monopoly Plus (Iris Plus 655 / Wine + DXVK)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109524">Bug 109524</a> - &quot;Invalid glsl version in shading_language_version()&quot; when trying to run directX games using wine</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110309">Bug 110309</a> - [icl][bisected] regression on piglit arb_gpu_shader_int 64.execution.fs-ishl-then-* tests</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110663">Bug 110663</a> - threads_posix.h:96: undefined reference to `pthread_once'</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110955">Bug 110955</a> - Mesa 18.2.8 implementation error: Invalid GLSL version in shading_language_version()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111010">Bug 111010</a> - Cemu Shader Cache Corruption Displaying Solid Color After commit 11e16ca7ce0</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111071">Bug 111071</a> - SPIR-V shader processing fails with message about &quot;extra dangling SSA sources&quot;</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111075">Bug 111075</a> - Processing of SPIR-V shader causes device hang, sometimes leading to system reboot</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111097">Bug 111097</a> - Can not detect VK_ERROR_OUT_OF_DATE_KHR or VK_SUBOPTIMAL_KHR when window resizing</li>
</ul>
<h2>Changes</h2>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Handle cmask being disallowed by addrlib.</li>
<li>anv: Add android dependencies on android.</li>
<li>radv: Only save the descriptor set if we have one.</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (2):</p>
<ul>
<li>anv: Fix pool allocator when first alloc needs to grow</li>
<li>spirv: Fix stride calculation when lowering Workgroup to offsets</li>
</ul>
<p>Chia-I Wu (2):</p>
<ul>
<li>anv: fix VkExternalBufferProperties for unsupported handles</li>
<li>anv: fix VkExternalBufferProperties for host allocation</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>nir: Add a helper to determine if an intrinsic can be reordered</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>radv: fix crash in shader tracing.</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>freedreno: Fix assertion failures in context setup in shader-db mode.</li>
</ul>
<p>Gert Wollny (1):</p>
<ul>
<li>softpipe: Remove unused static function</li>
</ul>
<p>Ian Romanick (4):</p>
<ul>
<li>intel/vec4: Reswizzle VF immediates too</li>
<li>nir: Add unit tests for nir_opt_comparison_pre</li>
<li>nir: Use nir_src_bit_size instead of alu1-&gt;dest.dest.ssa.bit_size</li>
<li>mesa: Set minimum possible GLSL version</li>
</ul>
<p>Jason Ekstrand (13):</p>
<ul>
<li>nir/instr_set: Expose nir_instrs_equal()</li>
<li>nir/loop_analyze: Fix phi-of-identical-alu detection</li>
<li>nir: Add more helpers for working with const values</li>
<li>nir/loop_analyze: Handle bit sizes correctly in calculate_iterations</li>
<li>nir/loop_analyze: Bail if we encounter swizzles</li>
<li>anv: Set Stateless Data Port Access MOCS</li>
<li>nir/opt_if: Clean up single-src phis in opt_if_loop_terminator</li>
<li>nir,intel: Add support for lowering 64-bit nir_opt_extract_*</li>
<li>anv: Account for dynamic stencil write disables in the PMA fix</li>
<li>nir/regs_to_ssa: Handle regs in phi sources properly</li>
<li>nir/loop_analyze: Refactor detection of limit vars</li>
<li>nir: Add some helpers for chasing SSA values properly</li>
<li>nir/loop_analyze: Properly handle swizzles in loop conditions</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>docs: add sha256 checksums for 19.1.2</li>
<li>Update version to 19.1.3</li>
</ul>
<p>Lepton Wu (1):</p>
<ul>
<li>virgl: Set meta data for textures from handle.</li>
</ul>
<p>Lionel Landwerlin (6):</p>
<ul>
<li>vulkan/overlay: fix command buffer stats</li>
<li>vulkan/overlay: fix crash on freeing NULL command buffer</li>
<li>anv: fix crash in vkCmdClearAttachments with unused attachment</li>
<li>vulkan/wsi: update swapchain status on vkQueuePresent</li>
<li>anv: report timestampComputeAndGraphics true</li>
<li>anv: fix format mapping for depth/stencil formats</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>radeonsi: don't set READ_ONLY for const_uploader to fix bindless texture hangs</li>
</ul>
<p>Samuel Iglesias Gonsálvez (1):</p>
<ul>
<li>anv: fix alphaToCoverage when there is no color attachment</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: fix VGT_GS_MODE if VS uses the primitive ID</li>
</ul>
<p>Sergii Romantsov (1):</p>
<ul>
<li>meta: memory leak of CopyPixels usage</li>
</ul>
<p>Timothy Arceri (1):</p>
<ul>
<li>mesa: save/restore SSO flag when using ARB_get_program_binary</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>meson: Add dep_thread dependency.</li>
</ul>
<p>Yevhenii Kolesnikov (1):</p>
<ul>
<li>meta: leaking of BO with DrawPixels</li>
</ul>
</div>
</body>
</html>
docs/relnotes/19.1.4.html 0 → 100644
View file @ 732a10e3
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.1.4 Release Notes / August 7, 2019</h1>
<p>
Mesa 19.1.4 is a bug fix release which fixes bugs found since the 19.1.3 release.
</p>
<p>
Mesa 19.1.4 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109203">Bug 109203</a> - [cfl dxvk] GPU Crash Launching Monopoly Plus (Iris Plus 655 / Wine + DXVK)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109524">Bug 109524</a> - &quot;Invalid glsl version in shading_language_version()&quot; when trying to run directX games using wine</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110309">Bug 110309</a> - [icl][bisected] regression on piglit arb_gpu_shader_int 64.execution.fs-ishl-then-* tests</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110663">Bug 110663</a> - threads_posix.h:96: undefined reference to `pthread_once'</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110955">Bug 110955</a> - Mesa 18.2.8 implementation error: Invalid GLSL version in shading_language_version()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111010">Bug 111010</a> - Cemu Shader Cache Corruption Displaying Solid Color After commit 11e16ca7ce0</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111071">Bug 111071</a> - SPIR-V shader processing fails with message about &quot;extra dangling SSA sources&quot;</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111075">Bug 111075</a> - Processing of SPIR-V shader causes device hang, sometimes leading to system reboot</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=111097">Bug 111097</a> - Can not detect VK_ERROR_OUT_OF_DATE_KHR or VK_SUBOPTIMAL_KHR when window resizing</li>
</ul>
<h2>Changes</h2>
<p>Andres Rodriguez (1):</p>
<ul>
<li>radv: fix queries with WAIT_BIT returning VK_NOT_READY</li>
</ul>
<p>Andrii Simiklit (2):</p>
<ul>
<li>intel/compiler: don't use a keyword struct for a class fs_reg</li>
<li>meson: add a warning for meson &lt; 0.46.0</li>
</ul>
<p>Arcady Goldmints-Orlov (1):</p>
<ul>
<li>anv: report HOST_ALLOCATION as supported for images</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Set correct metadata size for GFX9+.</li>
<li>radv: Take variable descriptor counts into account for buffer entries.</li>
<li>radv: Fix descriptor set allocation failure.</li>
</ul>
<p>Boyuan Zhang (4):</p>
<ul>
<li>radeon/uvd: fix poc for hevc encode</li>
<li>radeon/vcn: fix poc for hevc encode</li>
<li>radeon/uvd: enable rate control for hevc encoding</li>
<li>radeon/vcn: enable rate control for hevc encoding</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>anv: Remove special allocation for anv_push_constants</li>
</ul>
<p>Connor Abbott (1):</p>
<ul>
<li>nir: Allow qualifiers on copy_deref and image instructions</li>
</ul>
<p>Daniel Schürmann (1):</p>
<ul>
<li>spirv: Fix order of barriers in SpvOpControlBarrier</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>st/nir: fix arb fragment stage conversion</li>
</ul>
<p>Dylan Baker (1):</p>
<ul>
<li>meson: allow building all glx without any drivers</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>egl/drm: ensure the backing gbm is set before using it</li>
</ul>
<p>Eric Anholt (1):</p>
<ul>
<li>freedreno: Fix data races with allocating/freeing struct ir3.</li>
</ul>
<p>Eric Engestrom (5):</p>
<ul>
<li>nir: don't return void</li>
<li>util: fix no-op macro (bad number of arguments)</li>
<li>gallium+mesa: fix tgsi_semantic array type</li>
<li>scons+meson: suppress spammy build warning on MacOS</li>
<li>nir: remove explicit nir_intrinsic_index_flag values</li>
</ul>
<p>Francisco Jerez (1):</p>
<ul>
<li>intel/ir: Fix CFG corruption in opt_predicated_break().</li>
</ul>
<p>Ilia Mirkin (4):</p>
<ul>
<li>gallium/vl: fix compute tgsi shaders to not process undefined components</li>
<li>nv50,nvc0: update sampler/view bind functions to accept NULL array</li>
<li>nvc0: allow a non-user buffer to be bound at position 0</li>
<li>nv50/ir: handle insn not being there for definition of CVT arg</li>
</ul>
<p>Jason Ekstrand (6):</p>
<ul>
<li>intel/fs: Stop stack allocating large arrays</li>
<li>anv: Disable transform feedback on gen7</li>
<li>isl/formats: R8G8B8_UNORM_SRGB isn't supported on HSW</li>
<li>anv: Don't claim support for 24 and 48-bit formats on IVB</li>
<li>intel/fs: Use ALIGN16 instructions for all derivatives on gen &lt;= 7</li>
<li>intel/fs: Implement quad_swap_horizontal with a swizzle on gen7</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>docs: add sha256 checksums for 19.1.3</li>
<li>Update version to 19.1.4</li>
</ul>
<p>Kenneth Graunke (4):</p>
<ul>
<li>mesa: Fix ReadBuffers with pbuffers</li>
<li>egl: Quiet warning about front buffer rendering for pixmaps/pbuffers</li>
<li>egl: Make the 565 pbuffer-only config single buffered.</li>
<li>egl: Only expose 565 pbuffer configs if X can export them as DRI3 images</li>
</ul>
<p>Lionel Landwerlin (5):</p>
<ul>
<li>anv: fix use of comma operator</li>
<li>nir: add access to image_deref intrinsics</li>
<li>spirv: wrap push ssa/pointer values</li>
<li>spirv: propagate access qualifiers through ssa &amp; pointer</li>
<li>spirv: don't discard access set by vtn_pointer_dereference</li>
</ul>
<p>Mark Menzynski (1):</p>
<ul>
<li>nvc0/ir: Fix assert accessing null pointer</li>
</ul>
<p>Nataraj Deshpande (1):</p>
<ul>
<li>egl/android: Update color_buffers querying for buffer age</li>
</ul>
<p>Nicolas Dufresne (1):</p>
<ul>
<li>egl: Also query modifiers when exporting DMABuf</li>
</ul>
<p>Rhys Perry (1):</p>
<ul>
<li>ac/nir: fix txf_ms with an offset</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: fix crash in vkCmdClearAttachments with unused attachment</li>
</ul>
<p>Tapani Pälli (1):</p>
<ul>
<li>mesa: add glsl_type ref to one_time_init and decref to atexit</li>
</ul>
<p>Yevhenii Kolesnikov (1):</p>
<ul>
<li>main: Fix memleaks in mesa_use_program</li>
</ul>
</div>
</body>
</html>
meson.build
View file @ 732a10e3
......@@ -190,6 +190,12 @@ if cc.get_id() == 'intel'
endif
endif
#This message is needed until we bump meson version to 0.46 because of known 0.45.0 and 0.45.1 issue
#https://bugs.freedesktop.org/show_bug.cgi?id=109791
if meson.version().version_compare('< 0.46.0')
warning('''Meson < 0.46 doesn't automatically define `NDEBUG`; please update meson to at least 0.46.''')
endif
with_gallium = gallium_drivers.length() != 0 and gallium_drivers != ['']
if with_gallium and system_has_kms_drm
......@@ -244,6 +250,7 @@ endif
if host_machine.system() == 'darwin'
with_dri_platform = 'apple'
pre_args += '-DBUILDING_MESA'
elif ['windows', 'cygwin'].contains(host_machine.system())
with_dri_platform = 'windows'
elif system_has_kms_drm
......@@ -312,7 +319,7 @@ if with_glx == 'dri'
endif
endif
if not (with_dri or with_gallium or with_glx == 'xlib' or with_glx == 'gallium-xlib')
if not (with_dri or with_gallium or with_glx != 'disabled')
with_gles1 = false
with_gles2 = false
with_opengl = false
......@@ -379,9 +386,7 @@ if with_glx != 'disabled'
error('xlib conflicts with any dri driver')
endif
elif with_glx == 'dri'
if not with_dri
error('dri based GLX requires at least one DRI driver')
elif not with_shared_glapi
if not with_shared_glapi
error('dri based GLX requires shared-glapi')
endif
endif
......
scons/gallium.py
View file @ 732a10e3
......@@ -352,6 +352,7 @@ def generate(env):
'_DARWIN_C_SOURCE',
'GLX_USE_APPLEGL',
'GLX_DIRECT_RENDERING',
'BUILDING_MESA',
]
else:
cppdefines += [
......
src/amd/common/ac_nir_to_llvm.c
View file @ 732a10e3
......@@ -3747,7 +3747,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
goto write_result;
}
if (args.offset && instr->op != nir_texop_txf) {
if (args.offset && instr->op != nir_texop_txf && instr->op != nir_texop_txf_ms) {
LLVMValueRef offset[3], pack;
for (unsigned chan = 0; chan < 3; ++chan)
offset[chan] = ctx->ac.i32_0;
......@@ -3881,7 +3881,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
args.coords[sample_chan], fmask_ptr);
}
if (args.offset && instr->op == nir_texop_txf) {
if (args.offset && (instr->op == nir_texop_txf || instr->op == nir_texop_txf_ms)) {
int num_offsets = instr->src[offset_src].src.ssa->num_components;
num_offsets = MIN2(num_offsets, instr->coord_components);
for (unsigned i = 0; i < num_offsets; ++i) {
......
src/amd/vulkan/radv_descriptor_set.c
View file @ 732a10e3
......@@ -477,8 +477,17 @@ radv_descriptor_set_create(struct radv_device *device,
struct radv_descriptor_set **out_set)
{
struct radv_descriptor_set *set;
uint32_t buffer_count = layout->buffer_count;
if (variable_count) {
unsigned stride = 1;
if (layout->binding[layout->binding_count - 1].type == VK_DESCRIPTOR_TYPE_SAMPLER ||
layout->binding[layout->binding_count - 1].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT)
stride = 0;
buffer_count = layout->binding[layout->binding_count - 1].buffer_offset +
*variable_count * stride;
}
unsigned range_offset = sizeof(struct radv_descriptor_set) +
sizeof(struct radeon_winsys_bo *) * layout->buffer_count;
sizeof(struct radeon_winsys_bo *) * buffer_count;
unsigned mem_size = range_offset +
sizeof(struct radv_descriptor_range) * layout->dynamic_offset_count;
......@@ -787,9 +796,13 @@ VkResult radv_AllocateDescriptorSets(
pDescriptorSets[i] = radv_descriptor_set_to_handle(set);
}
if (result != VK_SUCCESS)
if (result != VK_SUCCESS) {
radv_FreeDescriptorSets(_device, pAllocateInfo->descriptorPool,
i, pDescriptorSets);
for (i = 0; i < pAllocateInfo->descriptorSetCount; i++) {
pDescriptorSets[i] = VK_NULL_HANDLE;
}
}
return result;
}
......
src/amd/vulkan/radv_image.c
View file @ 732a10e3
......@@ -729,7 +729,8 @@ radv_query_opaque_metadata(struct radv_device *device,
for (i = 0; i <= image->info.levels - 1; i++)
md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
md->size_metadata = (11 + image->info.levels - 1) * 4;
}
} else
md->size_metadata = 10 * 4;
}
void
......@@ -860,6 +861,11 @@ radv_image_alloc_cmask(struct radv_device *device,
uint32_t clear_value_size = 0;
radv_image_get_cmask_info(device, image, &image->cmask);
if (!image->cmask.size)
return;
assert(image->cmask.alignment);
image->cmask.offset = align64(image->size, image->cmask.alignment);
/* + 8 for storing the clear values */
if (!image->clear_value_offset) {
......
src/amd/vulkan/radv_meta.c
View file @ 732a10e3
......@@ -81,7 +81,7 @@ radv_meta_save(struct radv_meta_saved_state *state,
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
state->old_descriptor_set0 = descriptors_state->sets[0];
if (!state->old_descriptor_set0)
if (!(descriptors_state->valid & 1) || !state->old_descriptor_set0)
state->flags &= ~RADV_META_SAVE_DESCRIPTORS;
}
......
src/amd/vulkan/radv_meta_clear.c
View file @ 732a10e3
......@@ -1576,6 +1576,9 @@ emit_clear(struct radv_cmd_buffer *cmd_buffer,
emit_color_clear(cmd_buffer, clear_att, clear_rect, view_mask);
}
} else {
if (!subpass->depth_stencil_attachment)
return;
const uint32_t pass_att = subpass->depth_stencil_attachment->attachment;
if (pass_att == VK_ATTACHMENT_UNUSED)
return;
......
src/amd/vulkan/radv_nir_to_llvm.c
View file @ 732a10e3
......@@ -3610,9 +3610,10 @@ ac_setup_rings(struct radv_shader_context *ctx)
unsigned
radv_nir_get_max_workgroup_size(enum chip_class chip_class,
gl_shader_stage stage,
const struct nir_shader *nir)
{
switch (nir->info.stage) {
switch (stage) {
case MESA_SHADER_TESS_CTRL:
return chip_class >= CIK ? 128 : 64;
case MESA_SHADER_GEOMETRY:
......@@ -3623,6 +3624,8 @@ radv_nir_get_max_workgroup_size(enum chip_class chip_class,
return 0;
}
if (!nir)
return chip_class >= GFX9 ? 128 : 64;
unsigned max_workgroup_size = nir->info.cs.local_size[0] *
nir->info.cs.local_size[1] *
nir->info.cs.local_size[2];
......@@ -3689,6 +3692,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
for (int i = 0; i < shader_count; ++i) {
ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
radv_nir_get_max_workgroup_size(ctx.options->chip_class,
shaders[i]->info.stage,
shaders[i]));
}
......
src/amd/vulkan/radv_pipeline.c
View file @ 732a10e3
......@@ -2930,8 +2930,11 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
struct radv_pipeline *pipeline)
{
const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
uint32_t vgt_primitiveid_en = false;
const struct radv_shader_variant *vs =
pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
pipeline->shaders[MESA_SHADER_TESS_EVAL] :
pipeline->shaders[MESA_SHADER_VERTEX];
uint32_t vgt_gs_mode = 0;
if (radv_pipeline_has_gs(pipeline)) {
......@@ -2940,7 +2943,7 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
pipeline->device->physical_device->rad_info.chip_class);
} else if (outinfo->export_prim_id) {
} else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
vgt_primitiveid_en = true;
}
......
src/amd/vulkan/radv_private.h
View file @ 732a10e3
......@@ -1994,6 +1994,7 @@ void radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
const struct radv_nir_compiler_options *options);
unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,
gl_shader_stage stage,
const struct nir_shader *nir);
/* radv_shader_info.h */
......
src/amd/vulkan/radv_query.c
View file @ 732a10e3
......@@ -1139,7 +1139,7 @@ VkResult radv_GetQueryPoolResults(
if (flags & VK_QUERY_RESULT_WAIT_BIT) {
while (*(volatile uint64_t *)src == TIMESTAMP_NOT_READY)
;
available = *(uint64_t *)src != TIMESTAMP_NOT_READY;
available = true;
}
if (!available && !(flags & VK_QUERY_RESULT_PARTIAL_BIT))
......
src/amd/vulkan/radv_shader.c
View file @ 732a10e3
......@@ -765,7 +765,7 @@ generate_shader_stats(struct radv_device *device,
lds_increment);
} else if (stage == MESA_SHADER_COMPUTE) {
unsigned max_workgroup_size =
radv_nir_get_max_workgroup_size(chip_class, variant->nir);
radv_nir_get_max_workgroup_size(chip_class, stage, variant->nir);
lds_per_wave = (conf->lds_size * lds_increment) /
DIV_ROUND_UP(max_workgroup_size, 64);
}
......
src/compiler/nir/meson.build
View file @ 732a10e3
......@@ -299,4 +299,16 @@ if with_tests
link_with : libmesa_util,
)
)
test(
'comparison_pre',
executable(
'comparison_pre',
files('tests/comparison_pre_tests.cpp'),
c_args : [c_vis_args, c_msvc_compat_args, no_override_init_args],
include_directories : [inc_common],
dependencies : [dep_thread, idep_gtest, idep_nir],
link_with : libmesa_util,
)
)
endif
src/compiler/nir/nir.c
View file @ 732a10e3
......@@ -1204,6 +1204,41 @@ nir_foreach_src(nir_instr *instr, nir_foreach_src_cb cb, void *state)
return nir_foreach_dest(instr, visit_dest_indirect, &dest_state);
}
nir_const_value
nir_const_value_for_float(double f, unsigned bit_size)
{
nir_const_value v;
memset(&v, 0, sizeof(v));
switch (bit_size) {
case 16:
v.u16 = _mesa_float_to_half(f);
break;
case 32:
v.f32 = f;
break;
case 64:
v.f64 = f;
break;
default:
unreachable("Invalid bit size");
}
return v;
}
double
nir_const_value_as_float(nir_const_value value, unsigned bit_size)
{
switch (bit_size) {
case 16: return _mesa_half_to_float(value.u16);
case 32: return value.f32;
case 64: return value.f64;
default:
unreachable("Invalid bit size");
}
}
int64_t
nir_src_comp_as_int(nir_src src, unsigned comp)
{
......@@ -1997,6 +2032,8 @@ void
nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
bool bindless)
{
enum gl_access_qualifier access = nir_intrinsic_access(intrin);
switch (intrin->intrinsic) {
#define CASE(op) \
case nir_intrinsic_image_deref_##op: \
......@@ -2028,7 +2065,7 @@ nir_rewrite_image_intrinsic(nir_intrinsic_instr *intrin, nir_ssa_def *src,
nir_intrinsic_set_image_dim(intrin, glsl_get_sampler_dim(deref->type));
nir_intrinsic_set_image_array(intrin, glsl_sampler_type_is_array(deref->type));
nir_intrinsic_set_access(intrin, var->data.image.access);
nir_intrinsic_set_access(intrin, access | var->data.image.access);
nir_intrinsic_set_format(intrin, var->data.image.format);
nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
......
src/compiler/nir/nir.h
View file @ 732a10e3
......@@ -140,6 +140,106 @@ typedef union {
arr[i] = c[i].m; \
} while (false)
static inline nir_const_value
nir_const_value_for_raw_uint(uint64_t x, unsigned bit_size)
{
nir_const_value v;
memset(&v, 0, sizeof(v));
switch (bit_size) {
case 1: v.b = x; break;
case 8: v.u8 = x; break;
case 16: v.u16 = x; break;
case 32: v.u32 = x; break;
case 64: v.u64 = x; break;
default:
unreachable("Invalid bit size");
}
return v;
}
static inline nir_const_value
nir_const_value_for_int(int64_t i, unsigned bit_size)
{
nir_const_value v;
memset(&v, 0, sizeof(v));
assert(bit_size <= 64);
if (bit_size < 64) {
assert(i >= (-(1ll << (bit_size - 1))));
assert(i < (1ll << (bit_size - 1)));
}
return nir_const_value_for_raw_uint(i, bit_size);
}
static inline nir_const_value
nir_const_value_for_uint(uint64_t u, unsigned bit_size)
{
nir_const_value v;
memset(&v, 0, sizeof(v));
assert(bit_size <= 64);
if (bit_size < 64)
assert(u < (1ull << bit_size));
return nir_const_value_for_raw_uint(u, bit_size);
}
static inline nir_const_value
nir_const_value_for_bool(bool b, unsigned bit_size)
{
/* Booleans use a 0/-1 convention */
return nir_const_value_for_int(-(int)b, bit_size);
}
/* This one isn't inline because it requires half-float conversion */
nir_const_value nir_const_value_for_float(double b, unsigned bit_size);
static inline int64_t
nir_const_value_as_int(nir_const_value value, unsigned bit_size)
{
switch (bit_size) {
/* int1_t uses 0/-1 convention */
case 1: return -(int)value.b;
case 8: return value.i8;
case 16: return value.i16;
case 32: return value.i32;
case 64: return value.i64;
default:
unreachable("Invalid bit size");
}
}
static inline int64_t
nir_const_value_as_uint(nir_const_value value, unsigned bit_size)
{
switch (bit_size) {
case 1: return value.b;
case 8: return value.u8;
case 16: return value.u16;
case 32: return value.u32;
case 64: return value.u64;
default:
unreachable("Invalid bit size");
}
}
static inline bool
nir_const_value_as_bool(nir_const_value value, unsigned bit_size)
{
int64_t i = nir_const_value_as_int(value, bit_size);
/* Booleans of any size use 0/-1 convention */
assert(i == 0 || i == -1);
return i;
}
/* This one isn't inline because it requires half-float conversion */
double nir_const_value_as_float(nir_const_value value, unsigned bit_size);
typedef struct nir_constant {
/**
* Value of the constant.
......@@ -1281,6 +1381,10 @@ typedef enum {
*/
NIR_INTRINSIC_DESC_TYPE = 19,
/* Separate source/dest access flags for copies */
NIR_INTRINSIC_SRC_ACCESS,
NIR_INTRINSIC_DST_ACCESS,
NIR_INTRINSIC_NUM_INDEX_FLAGS,
} nir_intrinsic_index_flag;
......@@ -1381,6 +1485,8 @@ INTRINSIC_IDX_ACCESSORS(param_idx, PARAM_IDX, unsigned)
INTRINSIC_IDX_ACCESSORS(image_dim, IMAGE_DIM, enum glsl_sampler_dim)
INTRINSIC_IDX_ACCESSORS(image_array, IMAGE_ARRAY, bool)
INTRINSIC_IDX_ACCESSORS(access, ACCESS, enum gl_access_qualifier)
INTRINSIC_IDX_ACCESSORS(src_access, SRC_ACCESS, enum gl_access_qualifier)
INTRINSIC_IDX_ACCESSORS(dst_access, DST_ACCESS, enum gl_access_qualifier)
INTRINSIC_IDX_ACCESSORS(format, FORMAT, unsigned)
INTRINSIC_IDX_ACCESSORS(align_mul, ALIGN_MUL, unsigned)
INTRINSIC_IDX_ACCESSORS(align_offset, ALIGN_OFFSET, unsigned)
......@@ -1416,6 +1522,16 @@ nir_intrinsic_align(const nir_intrinsic_instr *intrin)
void nir_rewrite_image_intrinsic(nir_intrinsic_instr *instr,
nir_ssa_def *handle, bool bindless);
/* Determine if an intrinsic can be arbitrarily reordered and eliminated. */
static inline bool
nir_intrinsic_can_reorder(nir_intrinsic_instr *instr)
{
const nir_intrinsic_info *info =
&nir_intrinsic_infos[instr->intrinsic];
return (info->flags & NIR_INTRINSIC_CAN_ELIMINATE) &&
(info->flags & NIR_INTRINSIC_CAN_REORDER);
}
/**
* \group texture information
*
......@@ -1815,6 +1931,85 @@ NIR_DEFINE_CAST(nir_instr_as_parallel_copy, nir_instr,
nir_parallel_copy_instr, instr,
type, nir_instr_type_parallel_copy)
typedef struct {
nir_ssa_def *def;
unsigned comp;
} nir_ssa_scalar;
static inline bool
nir_ssa_scalar_is_const(nir_ssa_scalar s)
{
return s.def->parent_instr->type == nir_instr_type_load_const;
}
static inline nir_const_value
nir_ssa_scalar_as_const_value(nir_ssa_scalar s)
{
assert(s.comp < s.def->num_components);
nir_load_const_instr *load = nir_instr_as_load_const(s.def->parent_instr);
return load->value[s.comp];
}
#define NIR_DEFINE_SCALAR_AS_CONST(type, suffix) \
static inline type \
nir_ssa_scalar_as_##suffix(nir_ssa_scalar s) \
{ \
return nir_const_value_as_##suffix( \
nir_ssa_scalar_as_const_value(s), s.def->bit_size); \
}
NIR_DEFINE_SCALAR_AS_CONST(int64_t, int)
NIR_DEFINE_SCALAR_AS_CONST(uint64_t, uint)
NIR_DEFINE_SCALAR_AS_CONST(bool, bool)
NIR_DEFINE_SCALAR_AS_CONST(double, float)
#undef NIR_DEFINE_SCALAR_AS_CONST
static inline bool
nir_ssa_scalar_is_alu(nir_ssa_scalar s)
{
return s.def->parent_instr->type == nir_instr_type_alu;
}
static inline nir_op
nir_ssa_scalar_alu_op(nir_ssa_scalar s)
{
return nir_instr_as_alu(s.def->parent_instr)->op;
}
static inline nir_ssa_scalar
nir_ssa_scalar_chase_alu_src(nir_ssa_scalar s, unsigned alu_src_idx)
{
nir_ssa_scalar out = { NULL, 0 };
nir_alu_instr *alu = nir_instr_as_alu(s.def->parent_instr);
assert(alu_src_idx < nir_op_infos[alu->op].num_inputs);
/* Our component must be written */
assert(s.comp < s.def->num_components);
assert(alu->dest.write_mask & (1u << s.comp));
assert(alu->src[alu_src_idx].src.is_ssa);
out.def = alu->src[alu_src_idx].src.ssa;
if (nir_op_infos[alu->op].input_sizes[alu_src_idx] == 0) {
/* The ALU src is unsized so the source component follows the
* destination component.
*/
out.comp = alu->src[alu_src_idx].swizzle[s.comp];
} else {
/* This is a sized source so all source components work together to
* produce all the destination components. Since we need to return a
* scalar, this only works if the source is a scalar.
*/
assert(nir_op_infos[alu->op].input_sizes[alu_src_idx] == 1);
out.comp = alu->src[alu_src_idx].swizzle[0];
}
assert(out.comp < out.def->num_components);
return out;
}
/*
* Control flow
*
......@@ -2196,6 +2391,7 @@ typedef enum {
nir_lower_minmax64 = (1 << 10),
nir_lower_shift64 = (1 << 11),
nir_lower_imul_2x32_64 = (1 << 12),
nir_lower_extract64 = (1 << 13),
} nir_lower_int64_options;
typedef enum {
......@@ -2785,6 +2981,7 @@ NIR_SRC_AS_(deref, nir_deref_instr, nir_instr_type_deref, nir_instr_as_deref)
bool nir_src_is_dynamically_uniform(nir_src src);
bool nir_srcs_equal(nir_src src1, nir_src src2);
bool nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2);
void nir_instr_rewrite_src(nir_instr *instr, nir_src *src, nir_src new_src);
void nir_instr_move_src(nir_instr *dest_instr, nir_src *dest, nir_src *src);
void nir_if_rewrite_condition(nir_if *if_stmt, nir_src new_src);
......@@ -3487,6 +3684,9 @@ bool nir_lower_phis_to_regs_block(nir_block *block);
bool nir_lower_ssa_defs_to_regs_block(nir_block *block);
bool nir_rematerialize_derefs_in_use_blocks_impl(nir_function_impl *impl);
/* This is here for unit tests. */
bool nir_opt_comparison_pre_impl(nir_function_impl *impl);
bool nir_opt_comparison_pre(nir_shader *shader);
bool nir_opt_algebraic(nir_shader *shader);
......@@ -3535,6 +3735,7 @@ bool nir_opt_peephole_select(nir_shader *shader, unsigned limit,
bool indirect_load_ok, bool expensive_alu_ok);
bool nir_opt_remove_phis(nir_shader *shader);
bool nir_opt_remove_phis_block(nir_block *block);
bool nir_opt_shrink_load(nir_shader *shader);
......