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bin/.cherry-ignore
View file @ ede874c1
......@@ -23,6 +23,9 @@ e0c7114eb3c19d4c2653f661698a6baa3bc9bedf st/mesa: disable L3 thread pinning
b5f213bb1dcde22949dffe9d3a431fecd5d0f33b radv: binding streamout buffers doesn't change context regs
9367514524f70faad99c721bac92339c8ff8bad9 radeonsi: fix video APIs on Raven2
ea9f95e2a67eca90bb84eea24e7b4b804b3b1345 radeonsi: go back to using bottom-of-pipe for beginning of TIME_ELAPSED
8f401b0ce6e6650e1a85e9bb2be23d5ff08812b8 anv,radv: Disable VK_EXT_pci_bus_info
8c77f4c76ddfe0b692b430b012b65f6981a53336 meson: Add support for gnu hurd
7a90886921eb1d5d73b40aadd6fd3f340041bd26 meson: Add toggle for glx-direct
# fixes: This commit was reverted by commit 5f312e95f87.
a9031bf9b55602d93cccef6c926e2179c23205b4 i965/batch: avoid reverting batch buffer if saved state is an empty
# extra: intel/aub_viewer is not present in branch
......@@ -31,3 +34,23 @@ ac324a6809c09c54d3b0bfdb00e5e62987ec4ad8 intel/aub_viewer: fix dynamic state pri
# fixes: This commit requires commits 854202f70e6 and 84bc5738401 which did not
# land in branch.
c120dbfe4d18240315ecec9b43a61aeb9ab239ac mesa/main: fix incorrect depth-error
# fixes: This commit fixes commits b4476138d5ad and aa0fed10d357 which did not
# land in branch.
d0c7b079d07f751eb37ecaa45a2a6db920d71d7a freedreno: Fix autotools build.
# pick: While this commit does not include the proper CC tag, it was intended
# to be applied only in 18.3 branch.
017199d2d2e4c57015bc60edfcc656062c3a7472 mesa: Revert INTEL_fragment_shader_ordering support
# fixes: The changes this commit provides are already included in the branch.
ff6f1dd0d3c6b4c15ca51b478b2884d14f6a1e06 meson: libfreedreno depends upon libdrm (for fence support)
# fixes: This commit requires commits aeaf8dbd097 and 7484bc894b9 which did not
# land in branch.
f67dea5e19ef14187be0e8d0f61b1f764c7ccb4f radv: Fix multiview depth clears
# fixes: There is a specific patch for stable franch for this commit.
bde9f482de69528db5ccf5dd6bbfd8359adfbb19 ac: split 16-bit ssbo loads that may not be dword aligned
# pick: This commit is nominated to stable, but fixes commit b3c61469255 which
# is in 18.3 stable. Hence, this commit is considered as nominated to
# 18.3 stable.
947f7b452a550c66cfb9a8c9518e35635eb25947 nir: properly find the entry to keep in copy_prop_vars
# pick: This commit is nominated to stable, but fixes commit 11dc1307794 which
# is not in the current stable branch.
d6110d4d547ad98dce7a89d0e020ab5be5aaaad6 intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs
bin/get-pick-list.sh
View file @ ede874c1
......@@ -21,31 +21,46 @@ is_typod_nomination()
git show --summary "$1" | grep -q -i -o "CC:.*mesa-dev"
}
fixes=
# Helper to handle various mistypos of the fixes tag.
# The tag string itself is passed as argument and normalised within.
#
# Resulting string in the global variable "fixes" and contains entries
# in the form "fixes:$sha"
is_sha_nomination()
{
fixes=`git show --pretty=medium -s $1 | tr -d "\n" | \
sed -e 's/'"$2"'/\nfixes:/Ig' | \
grep -Eo 'fixes:[a-f0-9]{8,40}'`
fixes_count=`echo "$fixes" | wc -l`
fixes_count=`echo "$fixes" | grep "fixes:" | wc -l`
if test $fixes_count -eq 0; then
return 0
return 1
fi
# Throw a warning for each invalid sha
while test $fixes_count -gt 0; do
# Treat only the current line
id=`echo "$fixes" | tail -n $fixes_count | head -n 1 | cut -d : -f 2`
fixes_count=$(($fixes_count-1))
# Bail out if we cannot find suitable id.
# Any specific validation the $id is valid and not some junk, is
# implied with the follow up code
if test "x$id" = x; then
continue
if ! git show $id &>/dev/null; then
echo WARNING: Commit $1 lists invalid sha $id
fi
done
#Check if the offending commit is in branch.
return 0
}
# Checks if at least one of offending commits, listed in the global
# "fixes", is in branch.
sha_in_range()
{
fixes_count=`echo "$fixes" | grep "fixes:" | wc -l`
while test $fixes_count -gt 0; do
# Treat only the current line
id=`echo "$fixes" | tail -n $fixes_count | head -n 1 | cut -d : -f 2`
fixes_count=$(($fixes_count-1))
# Be that cherry-picked ...
# ... or landed before the branchpoint.
......@@ -103,20 +118,30 @@ do
continue
fi
if is_stable_nomination "$sha"; then
tag=stable
elif is_typod_nomination "$sha"; then
tag=typod
elif is_fixes_nomination "$sha"; then
if is_fixes_nomination "$sha"; then
tag=fixes
elif is_brokenby_nomination "$sha"; then
tag=brokenby
elif is_revert_nomination "$sha"; then
tag=revert
elif is_stable_nomination "$sha"; then
tag=stable
elif is_typod_nomination "$sha"; then
tag=typod
else
continue
fi
case "$tag" in
fixes | brokenby | revert )
if ! sha_in_range; then
continue
fi
;;
* )
;;
esac
printf "[ %8s ] " "$tag"
git --no-pager show --summary --oneline $sha
done
......
configure.ac
View file @ ede874c1
......@@ -1698,6 +1698,8 @@ xdri)
if test x"$enable_dri" = xyes; then
dri_modules="$dri_modules xcb-dri2 >= $XCBDRI2_REQUIRED"
fi
dri_modules="$dri_modules xxf86vm"
fi
if test x"$dri_platform" = xapple ; then
DEFINES="$DEFINES -DGLX_USE_APPLEGL"
......@@ -1707,8 +1709,6 @@ xdri)
fi
fi
dri_modules="$dri_modules xxf86vm"
PKG_CHECK_MODULES([DRIGL], [$dri_modules])
GL_PC_REQ_PRIV="$GL_PC_REQ_PRIV $dri_modules"
X11_INCLUDES="$X11_INCLUDES $DRIGL_CFLAGS"
......
debian/changelog
View file @ ede874c1
mesa (18.2.8-2~bpo9+1) stretch-backports; urgency=medium
* Rebuild for stretch-backports.
* Use libsensors4-dev build-dep again.
-- Andreas Boll <aboll@debian.org> Thu, 17 Jan 2019 17:03:56 +0100
mesa (18.2.8-2) unstable; urgency=medium
* Actually merge the upstream version. (Closes: #917556)
-- Timo Aaltonen <tjaalton@debian.org> Fri, 28 Dec 2018 20:11:40 +0200
mesa (18.2.8-1) unstable; urgency=medium
* New upstream release.
* control: Build-depend on libsensors-dev. (Closes: #917442)
-- Timo Aaltonen <tjaalton@debian.org> Fri, 28 Dec 2018 10:50:13 +0200
mesa (18.2.7-2) unstable; urgency=medium
* Temporarily disable libsensors support to bootstrap with libsensors5.
-- Emilio Pozuelo Monfort <pochu@debian.org> Fri, 21 Dec 2018 09:22:16 +0100
mesa (18.2.7-1) unstable; urgency=medium
* New upstream release.
-- Timo Aaltonen <tjaalton@debian.org> Wed, 19 Dec 2018 11:47:32 +0200
mesa (18.2.6-1~bpo9+1) stretch-backports; urgency=medium
* Rebuild for stretch-backports.
......
docs/relnotes/18.2.6.html
View file @ ede874c1
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
e0ea1236dbc6c412b02e1b5d7f838072525971a6630246fa82ae4466a6d8a587 mesa-18.2.6.tar.gz
9ebafa4f8249df0c718e93b9ca155e3593a1239af303aa2a8b0f2056a7efdc12 mesa-18.2.6.tar.xz
</pre>
......
docs/relnotes/18.2.7.html 0 → 100644
View file @ ede874c1
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.7 Release Notes / December 13, 2018</h1>
<p>
Mesa 18.2.7 is a bug fix release which fixes bugs found since the 18.2.6 release.
</p>
<p>
Mesa 18.2.7 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
092351cfbcd430ec595fbd3a3d8d253fd62c29074e1740d7198b00289ab400f8 mesa-18.2.7.tar.gz
9c7b02560d89d77ca279cd21f36ea9a49e9ffc5611f6fe35099357d744d07ae6 mesa-18.2.7.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106577">Bug 106577</a> - broken rendering with nine and nouveau (GM107)</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108245">Bug 108245</a> - RADV/Vega: Low mip levels of large BCn textures get corrupted by vkCmdCopyBufferToImage</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108311">Bug 108311</a> - Query buffer object support is broken on r600.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108894">Bug 108894</a> - [anv] vkCmdCopyBuffer() and vkCmdCopyQueryPoolResults() write-after-write hazard</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108909">Bug 108909</a> - Vkd3d test failure test_resolve_non_issued_query_data()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108914">Bug 108914</a> - blocky shadow artifacts in The Forest with DXVK, RADV_DEBUG=nohiz fixes this</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108925">Bug 108925</a> - vkCmdCopyQueryPoolResults(VK_QUERY_RESULT_WAIT_BIT) for timestamps with large query count hangs</li>
</ul>
<h2>Changes</h2>
<p>Alex Smith (1):</p>
<ul>
<li>radv: Flush before vkCmdWriteTimestamp() if needed</li>
</ul>
<p>Bas Nieuwenhuizen (4):</p>
<ul>
<li>radv: Align large buffers to the fragment size.</li>
<li>radv: Clamp gfx9 image view extents to the allocated image extents.</li>
<li>radv/android: Mark android WSI image as shareable.</li>
<li>radv/android: Use buffer metadata to determine scanout compat.</li>
</ul>
<p>Dave Airlie (2):</p>
<ul>
<li>r600: make suballocator 256-bytes align</li>
<li>radv: use 3d shader for gfx9 copies if dst is 3d</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>egl/wayland: bail out when drmGetMagic fails</li>
<li>egl/wayland: plug memory leak in drm_handle_device()</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>v3d: Fix a leak of the transfer helper on screen destroy.</li>
<li>vc4: Fix a leak of the transfer helper on screen destroy.</li>
<li>v3d: Fix a leak of the disassembled instruction string during debug dumps.</li>
</ul>
<p>Eric Engestrom (3):</p>
<ul>
<li>anv: correctly use vulkan 1.0 by default</li>
<li>wsi/display: fix mem leak when freeing swapchains</li>
<li>vulkan/wsi: fix s/,/;/ typo</li>
</ul>
<p>Gurchetan Singh (3):</p>
<ul>
<li>virgl: quadruple command buffer size</li>
<li>virgl: avoid large inline transfers</li>
<li>virgl: don't mark buffers as unclean after a write</li>
</ul>
<p>Juan A. Suarez Romero (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.6</li>
<li>cherry-ignore: freedreno: Fix autotools build.</li>
<li>cherry-ignore: mesa: Revert INTEL_fragment_shader_ordering support</li>
<li>Update version to 18.2.7</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nv50,nvc0: Fix gallium nine regression regarding sampler bindings</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>anv: flush pipeline before query result copies</li>
<li>anv/query: flush render target before copying results</li>
</ul>
<p>Michal Srb (2):</p>
<ul>
<li>gallium: Constify drisw_loader_funcs struct</li>
<li>drisw: Use separate drisw_loader_funcs for shm</li>
</ul>
<p>Nicolai Hähnle (2):</p>
<ul>
<li>egl/wayland: rather obvious build fix</li>
<li>meson: link LLVM 'native' component when LLVM is available</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: rework the TC-compat HTILE hardware bug with COND_EXEC</li>
</ul>
<p>Thomas Hellstrom (2):</p>
<ul>
<li>st/xa: Fix a memory leak</li>
<li>winsys/svga: Fix a memory leak</li>
</ul>
<p>Tobias Klausmann (1):</p>
<ul>
<li>amd/vulkan: meson build - use radv_deps for libvulkan_radeon</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>st/xvmc: Add X11 include path.</li>
</ul>
</div>
</body>
</html>
docs/relnotes/18.2.8.html 0 → 100644
View file @ ede874c1
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.2.8 Release Notes / December 27, 2018</h1>
<p>
Mesa 18.2.8 is a bug fix release which fixes bugs found since the 18.2.7 release.
</p>
<p>
Mesa 18.2.8 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108114">Bug 108114</a> - [vulkancts] new VK_KHR_16bit_storage tests fail.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108116">Bug 108116</a> - [vulkancts] stencil partial clear tests fail.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108910">Bug 108910</a> - Vkd3d test failure test_multisample_array_texture()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108911">Bug 108911</a> - Vkd3d test failure test_clear_render_target_view()</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109081">Bug 109081</a> - [bisected] [HSW] Regression in clipping.user_defined.clip_* vulkancts tests</li>
</ul>
<h2>Changes</h2>
<p>Alex Deucher (3):</p>
<ul>
<li>pci_ids: add new vega10 pci ids</li>
<li>pci_ids: add new vega20 pci id</li>
<li>pci_ids: add new VegaM pci id</li>
</ul>
<p>Axel Davy (3):</p>
<ul>
<li>st/nine: Fix volumetexture dtor on ctor failure</li>
<li>st/nine: Bind src not dst in nine_context_box_upload</li>
<li>st/nine: Add src reference to nine_context_range_upload</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>nir: properly clear the entry sources in copy_prop_vars</li>
</ul>
<p>Dylan Baker (1):</p>
<ul>
<li>meson: Fix ppc64 little endian detection</li>
</ul>
<p>Emil Velikov (9):</p>
<ul>
<li>glx: mandate xf86vidmode only for "drm" dri platforms</li>
<li>bin/get-pick-list.sh: rework handing of sha nominations</li>
<li>bin/get-pick-list.sh: warn when commit lists invalid sha</li>
<li>meson: don't require glx/egl/gbm with gallium drivers</li>
<li>pipe-loader: meson: reference correct library</li>
<li>TODO: glx: meson: build dri based glx tests, only with -Dglx=dri</li>
<li>glx: meson: drop includes from a link-only library</li>
<li>glx: meson: wire up the dispatch-index-check test</li>
<li>glx/test: meson: assorted include fixes</li>
</ul>
<p>Eric Anholt (2):</p>
<ul>
<li>v3d: Make sure that a thrsw doesn't split a multop from its umul24.</li>
<li>v3d: Add missing flagging of SYNCB as a TSY op.</li>
</ul>
<p>Erik Faye-Lund (2):</p>
<ul>
<li>virgl: wrap vertex element state in a struct</li>
<li>virgl: work around bad assumptions in virglrenderer</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>intel/compiler: do not copy-propagate strided regions to ddx/ddy arguments</li>
</ul>
<p>Ian Romanick (2):</p>
<ul>
<li>i965/vec4/dce: Don't narrow the write mask if the flags are used</li>
<li>Revert "nir/lower_indirect: Bail early if modes == 0"</li>
</ul>
<p>Jan Vesely (1):</p>
<ul>
<li>clover: Fix build after clang r348827</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>nir/constant_folding: Fix source bit size logic</li>
</ul>
<p>Jon Turney (1):</p>
<ul>
<li>glx: Fix compilation with GLX_USE_WINDOWSGL</li>
</ul>
<p>Juan A. Suarez Romero (7):</p>
<ul>
<li>docs: add sha256 checksums for 18.2.7</li>
<li>cherry-ignore: add explicit 18.3 only nominations</li>
<li>cherry-ignore: meson: libfreedreno depends upon libdrm (for fence support)</li>
<li>cherry-ignore: radv: Fix multiview depth clears</li>
<li>cherry-ignore: nir: properly find the entry to keep in copy_prop_vars</li>
<li>cherry-ignore: intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs</li>
<li>Update version to 18.2.8</li>
</ul>
<p>Kirill Burtsev (1):</p>
<ul>
<li>loader: free error state, when checking the drawable type</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv: don't do partial resolve on layer &gt; 0</li>
</ul>
<p>Rhys Perry (2):</p>
<ul>
<li>radv: don't set surf_index for stencil-only images</li>
<li>ac: split 16-bit ssbo loads that may not be dword aligned</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>mesa/st/nir: fix missing nir_compact_varyings</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: switch on EOP when primitive restart is enabled with triangle strips</li>
</ul>
<p>Vinson Lee (2):</p>
<ul>
<li>meson: Fix typo.</li>
<li>meson: Fix libsensors detection.</li>
</ul>
</div>
</body>
</html>
include/pci_ids/radeonsi_pci_ids.h
View file @ ede874c1
......@@ -219,6 +219,7 @@ CHIPSET(0x699F, POLARIS12)
CHIPSET(0x694C, VEGAM)
CHIPSET(0x694E, VEGAM)
CHIPSET(0x694F, VEGAM)
CHIPSET(0x6860, VEGA10)
CHIPSET(0x6861, VEGA10)
......@@ -227,8 +228,14 @@ CHIPSET(0x6863, VEGA10)
CHIPSET(0x6864, VEGA10)
CHIPSET(0x6867, VEGA10)
CHIPSET(0x6868, VEGA10)
CHIPSET(0x687F, VEGA10)
CHIPSET(0x6869, VEGA10)
CHIPSET(0x686A, VEGA10)
CHIPSET(0x686B, VEGA10)
CHIPSET(0x686C, VEGA10)
CHIPSET(0x686D, VEGA10)
CHIPSET(0x686E, VEGA10)
CHIPSET(0x686F, VEGA10)
CHIPSET(0x687F, VEGA10)
CHIPSET(0x69A0, VEGA12)
CHIPSET(0x69A1, VEGA12)
......@@ -240,6 +247,7 @@ CHIPSET(0x66A0, VEGA20)
CHIPSET(0x66A1, VEGA20)
CHIPSET(0x66A2, VEGA20)
CHIPSET(0x66A3, VEGA20)
CHIPSET(0x66A4, VEGA20)
CHIPSET(0x66A7, VEGA20)
CHIPSET(0x66AF, VEGA20)
......
meson.build
View file @ ede874c1
......@@ -379,9 +379,9 @@ endif
if with_any_vk and (with_platform_x11 and not with_dri3)
error('Vulkan drivers require dri3 for X11 support')
endif
if with_dri or with_gallium
if with_glx == 'disabled' and not with_egl and not with_platform_haiku
error('building dri or gallium drivers require at least one window system')
if with_dri
if with_glx == 'disabled' and not with_egl and not with_gbm
error('building dri drivers require at least one windowing system')
endif
endif
......@@ -611,7 +611,7 @@ if with_gallium_st_nine
error('The nine state tracker requires gallium softpipe/llvmpipe.')
elif not (with_gallium_radeonsi or with_gallium_nouveau or with_gallium_r600
or with_gallium_r300 or with_gallium_svga or with_gallium_i915)
error('The nine state tracker requires at least on non-swrast gallium driver.')
error('The nine state tracker requires at least one non-swrast gallium driver.')
endif
if not with_dri3
error('Using nine with wine requires dri3')
......@@ -619,7 +619,12 @@ if with_gallium_st_nine
endif
if get_option('power8') != 'false'
if host_machine.cpu_family() == 'ppc64le'
# on old versions of meson the cpu family would return as ppc64le on little
# endian power8, this was changed in 0.48 such that the family would always
# be ppc64 regardless of endianness, and the the machine.endian() value
# should be checked. Since we support versions < 0.48 we need to use
# startswith.
if host_machine.cpu_family().startswith('ppc64') and host_machine.endian() == 'little'
if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.8')
error('Altivec is not supported with gcc version < 4.8.')
endif
......@@ -949,7 +954,7 @@ if with_asm
with_asm_arch = 'sparc'
pre_args += ['-DUSE_SPARC_ASM']
endif
elif host_machine.cpu_family() == 'ppc64le'
elif host_machine.cpu_family().startswith('ppc64') and host_machine.endian() == 'little'
if system_has_kms_drm
with_asm_arch = 'ppc64le'
pre_args += ['-DUSE_PPC64LE_ASM']
......@@ -1139,7 +1144,7 @@ endif
llvm_modules = ['bitwriter', 'engine', 'mcdisassembler', 'mcjit']
llvm_optional_modules = []
if with_amd_vk or with_gallium_radeonsi or with_gallium_r600
llvm_modules += ['amdgpu', 'bitreader', 'ipo']
llvm_modules += ['amdgpu', 'native', 'bitreader', 'ipo']
if with_gallium_r600
llvm_modules += 'asmparser'
endif
......@@ -1330,7 +1335,6 @@ if with_platform_x11
dep_xdamage = dependency('xdamage', version : '>= 1.1')
dep_xfixes = dependency('xfixes')
dep_xcb_glx = dependency('xcb-glx', version : '>= 1.8.1')
dep_xxf86vm = dependency('xxf86vm')
endif
if (with_any_vk or with_glx == 'dri' or
(with_gallium_vdpau or with_gallium_xvmc or with_gallium_va or
......@@ -1357,6 +1361,7 @@ if with_platform_x11
if with_glx == 'dri'
if with_dri_platform == 'drm'
dep_dri2proto = dependency('dri2proto', version : '>= 2.8')
dep_xxf86vm = dependency('xxf86vm')
endif
dep_glproto = dependency('glproto', version : '>= 1.4.14')
endif
......@@ -1377,7 +1382,7 @@ endif
_sensors = get_option('lmsensors')
if _sensors != 'false'
dep_lmsensors = cc.find_library('libsensors', required : _sensors == 'true')
dep_lmsensors = cc.find_library('sensors', required : _sensors == 'true')
if dep_lmsensors.found()
pre_args += '-DHAVE_LIBSENSORS=1'
endif
......@@ -1407,9 +1412,9 @@ elif with_glx == 'dri'
'xcb-glx >= 1.8.1']
if with_dri_platform == 'drm'
gl_priv_reqs += 'xcb-dri2 >= 1.8'
endif
gl_priv_reqs += 'xxf86vm'
endif
endif
if dep_libdrm.found()
gl_priv_reqs += 'libdrm >= 2.4.75'
endif
......
src/amd/common/ac_llvm_build.c
View file @ ede874c1
......@@ -2729,9 +2729,11 @@ LLVMValueRef ac_trim_vector(struct ac_llvm_context *ctx, LLVMValueRef value,
if (count == num_components)
return value;
LLVMValueRef masks[] = {
LLVMConstInt(ctx->i32, 0, false), LLVMConstInt(ctx->i32, 1, false),
LLVMConstInt(ctx->i32, 2, false), LLVMConstInt(ctx->i32, 3, false)};
LLVMValueRef masks[MAX2(count, 2)];
masks[0] = ctx->i32_0;
masks[1] = ctx->i32_1;
for (unsigned i = 2; i < count; i++)
masks[i] = LLVMConstInt(ctx->i32, i, false);
if (count == 1)
return LLVMBuildExtractElement(ctx->builder, value, masks[0],
......
src/amd/common/ac_nir_to_llvm.c
View file @ ede874c1
......@@ -1621,31 +1621,39 @@ static LLVMValueRef visit_atomic_ssbo(struct ac_nir_context *ctx,
static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMValueRef results[2];
int load_bytes;
int elem_size_bytes = instr->dest.ssa.bit_size / 8;
int num_components = instr->num_components;
int num_bytes = num_components * elem_size_bytes;
for (int i = 0; i < num_bytes; i += load_bytes) {
load_bytes = MIN2(num_bytes - i, 16);
const char *load_name;
LLVMTypeRef data_type;
LLVMValueRef offset = get_src(ctx, instr->src[1]);
LLVMValueRef immoffset = LLVMConstInt(ctx->ac.i32, i, false);
LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi,
get_src(ctx, instr->src[0]), false);
LLVMValueRef vindex = ctx->ac.i32_0;
int idx = i ? 1 : 0;
LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.ssa);
LLVMTypeRef def_elem_type = num_components > 1 ? LLVMGetElementType(def_type) : def_type;
LLVMValueRef results[4];
for (int i = 0; i < num_components;) {
int num_elems = num_components - i;
if (elem_size_bytes < 4)
num_elems = 1;
if (num_elems * elem_size_bytes > 16)
num_elems = 16 / elem_size_bytes;
int load_bytes = num_elems * elem_size_bytes;
LLVMValueRef immoffset = LLVMConstInt(ctx->ac.i32, i * elem_size_bytes, false);
LLVMValueRef ret;
if (load_bytes == 2) {
results[idx] = ac_build_tbuffer_load_short(&ctx->ac,
ret = ac_build_tbuffer_load_short(&ctx->ac,
rsrc,
vindex,
offset,
ctx->ac.i32_0,
immoffset);
} else {
const char *load_name;
LLVMTypeRef data_type;
switch (load_bytes) {
case 16:
case 12:
......@@ -1671,33 +1679,23 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx,
ctx->ac.i1false,
ctx->ac.i1false,
};
results[idx] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
unsigned num_elems = ac_get_type_size(data_type) / elem_size_bytes;
LLVMTypeRef resTy = LLVMVectorType(LLVMIntTypeInContext(ctx->ac.context, instr->dest.ssa.bit_size), num_elems);
results[idx] = LLVMBuildBitCast(ctx->ac.builder, results[idx], resTy, "");
}
ret = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0);
}
assume(results[0]);
LLVMValueRef ret = results[0];
if (num_bytes > 16 || num_components == 3) {
LLVMValueRef masks[] = {
LLVMConstInt(ctx->ac.i32, 0, false), LLVMConstInt(ctx->ac.i32, 1, false),
LLVMConstInt(ctx->ac.i32, 2, false), LLVMConstInt(ctx->ac.i32, 3, false),
};
LLVMTypeRef byte_vec = LLVMVectorType(ctx->ac.i8, ac_get_type_size(LLVMTypeOf(ret)));
ret = LLVMBuildBitCast(ctx->ac.builder, ret, byte_vec, "");
ret = ac_trim_vector(&ctx->ac, ret, load_bytes);
if (num_bytes > 16 && num_components == 3) {
/* we end up with a v2i64 and i64 but shuffle fails on that */
results[1] = ac_build_expand(&ctx->ac, results[1], 1, 2);
}
LLVMTypeRef ret_type = LLVMVectorType(def_elem_type, num_elems);
ret = LLVMBuildBitCast(ctx->ac.builder, ret, ret_type, "");
LLVMValueRef swizzle = LLVMConstVector(masks, num_components);
ret = LLVMBuildShuffleVector(ctx->ac.builder, results[0],
results[num_bytes > 16 ? 1 : 0], swizzle, "");
for (unsigned j = 0; j < num_elems; j++) {
results[i + j] = LLVMBuildExtractElement(ctx->ac.builder, ret, LLVMConstInt(ctx->ac.i32, j, false), "");
}
i += num_elems;
}
return LLVMBuildBitCast(ctx->ac.builder, ret,
get_def_type(ctx, &instr->dest.ssa), "");
return ac_build_gather_values(&ctx->ac, results, num_components);
}
static LLVMValueRef visit_load_ubo_buffer(struct ac_nir_context *ctx,
......
src/amd/vulkan/meson.build
View file @ ede874c1
......@@ -140,7 +140,7 @@ libvulkan_radeon = shared_library(
],
dependencies : [
dep_llvm, dep_libdrm_amdgpu, dep_thread, dep_elf, dep_dl, dep_m,
dep_valgrind,
dep_valgrind, radv_deps,
idep_nir,
],
c_args : [c_vis_args, no_override_init_args, radv_flags],
......
src/amd/vulkan/radv_android.c
View file @ ede874c1
......@@ -110,17 +110,6 @@ radv_image_from_gralloc(VkDevice device_h,
struct radv_bo *bo = NULL;
VkResult result;
result = radv_image_create(device_h,
&(struct radv_image_create_info) {
.vk_info = base_info,
.scanout = true,
.no_metadata_planes = true},
alloc,
&image_h);
if (result != VK_SUCCESS)
return result;
if (gralloc_info->handle->numFds != 1) {
return vk_errorf(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR,
"VkNativeBufferANDROID::handle::numFds is %d, "
......@@ -133,23 +122,14 @@ radv_image_from_gralloc(VkDevice device_h,
*/
int dma_buf = gralloc_info->handle->data[0];
image = radv_image_from_handle(image_h);
VkDeviceMemory memory_h;
const VkMemoryDedicatedAllocateInfoKHR ded_alloc = {
.sType = VK_STRUCTURE_TYPE_MEMORY_DEDICATED_ALLOCATE_INFO_KHR,
.pNext = NULL,
.buffer = VK_NULL_HANDLE,
.image = image_h
};
const VkImportMemoryFdInfoKHR import_info = {
.sType = VK_STRUCTURE_TYPE_IMPORT_MEMORY_FD_INFO_KHR,
.pNext = &ded_alloc,
.handleType = VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR,
.fd = dup(dma_buf),
};
/* Find the first VRAM memory type, or GART for PRIME images. */
int memory_type_index = -1;
for (int i = 0; i < device->physical_device->memory_properties.memoryTypeCount; ++i) {
......@@ -168,14 +148,49 @@ radv_image_from_gralloc(VkDevice device_h,
&(VkMemoryAllocateInfo) {
.sType = VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO,
.pNext = &import_info,
.allocationSize = image->size,
/* Max buffer size, unused for imports */
.allocationSize = 0x7FFFFFFF,
.memoryTypeIndex = memory_type_index,
},
alloc,
&memory_h);
if (result != VK_SUCCESS)
return result;
struct radeon_bo_metadata md;
device->ws->buffer_get_metadata(radv_device_memory_from_handle(memory_h)->bo, &md);
bool is_scanout;
if (device->physical_device->rad_info.chip_class >= GFX9) {
/* Copied from radeonsi, but is hacky so should be cleaned up. */
is_scanout = md.u.gfx9.swizzle_mode == 0 || md.u.gfx9.swizzle_mode % 4 == 2;
} else {
is_scanout = md.u.legacy.scanout;
}
VkImageCreateInfo updated_base_info = *base_info;
VkExternalMemoryImageCreateInfo external_memory_info = {
.sType = VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_IMAGE_CREATE_INFO,
.pNext = updated_base_info.pNext,
.handleTypes = VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT,
};
updated_base_info.pNext = &external_memory_info;
result = radv_image_create(device_h,
&(struct radv_image_create_info) {
.vk_info = &updated_base_info,
.scanout = is_scanout,
.no_metadata_planes = true},
alloc,
&image_h);
if (result != VK_SUCCESS)
goto fail_create_image;
image = radv_image_from_handle(image_h);
radv_BindImageMemory(device_h, image_h, memory_h, 0);
image->owned_memory = memory_h;
......@@ -185,9 +200,7 @@ radv_image_from_gralloc(VkDevice device_h,
return VK_SUCCESS;
fail_create_image:
fail_size:
radv_DestroyImage(device_h, image_h, alloc);
radv_FreeMemory(device_h, memory_h, alloc);
return result;
}
......
src/amd/vulkan/radv_cmd_buffer.c
View file @ ede874c1
......@@ -1051,7 +1051,7 @@ static void
radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
struct radv_ds_buffer_info *ds,
struct radv_image *image, VkImageLayout layout,
bool requires_cond_write)
bool requires_cond_exec)
{
uint32_t db_z_info = ds->db_z_info;
uint32_t db_z_info_reg;
......@@ -1075,39 +1075,22 @@ radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
}
/* When we don't know the last fast clear value we need to emit a
* conditional packet, otherwise we can update DB_Z_INFO directly.
* conditional packet that will eventually skip the following
* SET_CONTEXT_REG packet.
*/
if (requires_cond_write) {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
const uint32_t write_space = 0 << 8; /* register */
const uint32_t poll_space = 1 << 4; /* memory */
const uint32_t function = 3 << 0; /* equal to the reference */
const uint32_t options = write_space | poll_space | function;
radeon_emit(cmd_buffer->cs, options);
/* poll address - location of the depth clear value */
if (requires_cond_exec) {
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->clear_value_offset;
/* In presence of stencil format, we have to adjust the base
* address because the first value is the stencil clear value.
*/
if (vk_format_is_stencil(image->vk_format))
va += 4;
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
radeon_emit(cmd_buffer->cs, va);
radeon_emit(cmd_buffer->cs, va >> 32);
radeon_emit(cmd_buffer->cs, 0);
radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
}
radeon_emit(cmd_buffer->cs, fui(0.0f)); /* reference value */
radeon_emit(cmd_buffer->cs, (uint32_t)-1); /* comparison mask */
radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
radeon_emit(cmd_buffer->cs, 0u); /* write address high */
radeon_emit(cmd_buffer->cs, db_z_info);
} else {
radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
}
}
static void
radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
......@@ -1253,6 +1236,45 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cs, fui(ds_clear_value.depth));
}
/**
* Update the TC-compat metadata value for this image.
*/
static void
radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
uint32_t value)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, value);
}
static void
radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image,
VkClearDepthStencilValue ds_clear_value)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
uint32_t cond_val;
/* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
* depth clear value is 0.0f.
*/
cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
}
/**
* Update the clear depth/stencil values for this image.
*/
......@@ -1266,6 +1288,12 @@ radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
if (radv_image_is_tc_compat_htile(image) &&
(aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
ds_clear_value);
}
radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
aspects);
}
......@@ -4046,6 +4074,15 @@ static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
if (radv_image_is_tc_compat_htile(image)) {
/* Initialize the TC-compat metada value to 0 because by
* default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
* need have to conditionally update its value when performing
* a fast depth clear.
*/
radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
}
}
static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
......
src/amd/vulkan/radv_image.c
View file @ ede874c1
......@@ -853,6 +853,14 @@ radv_image_alloc_htile(struct radv_image *image)
/* + 8 for storing the clear values */
image->clear_value_offset = image->htile_offset + image->surface.htile_size;
image->size = image->clear_value_offset + 8;
if (radv_image_is_tc_compat_htile(image)) {
/* Metadata for the TC-compatible HTILE hardware bug which
* have to be fixed by updating ZRANGE_PRECISION when doing
* fast depth clears to 0.0f.
*/
image->tc_compat_zrange_offset = image->clear_value_offset + 8;
image->size = image->clear_value_offset + 16;
}
image->alignment = align64(image->alignment, image->surface.htile_alignment);
}
......@@ -958,7 +966,7 @@ radv_image_create(VkDevice _device,
image->shareable = vk_find_struct_const(pCreateInfo->pNext,
EXTERNAL_MEMORY_IMAGE_CREATE_INFO_KHR) != NULL;
if (!vk_format_is_depth(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
image->info.surf_index = &device->image_mrt_offset_counter;
}
......@@ -995,8 +1003,8 @@ radv_image_create(VkDevice _device,
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
radv_image_alloc_htile(image);
image->tc_compatible_htile = image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
radv_image_alloc_htile(image);
} else {
image->surface.htile_size = 0;
}
......@@ -1156,8 +1164,6 @@ radv_image_view_init(struct radv_image_view *iview,
if (device->physical_device->rad_info.chip_class >= GFX9 &&
vk_format_is_compressed(image->vk_format) &&
!vk_format_is_compressed(iview->vk_format)) {
unsigned rounded_img_w = util_next_power_of_two(iview->extent.width);
unsigned rounded_img_h = util_next_power_of_two(iview->extent.height);
unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
......@@ -1167,8 +1173,8 @@ radv_image_view_init(struct radv_image_view *iview,
lvl_width <<= range->baseMipLevel;
lvl_height <<= range->baseMipLevel;
iview->extent.width = CLAMP(lvl_width, iview->extent.width, rounded_img_w);
iview->extent.height = CLAMP(lvl_height, iview->extent.height, rounded_img_h);
iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->surface.u.gfx9.surf_pitch);
iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->surface.u.gfx9.surf_height);
}
}
......
src/amd/vulkan/radv_meta_bufimage.c
View file @ ede874c1
......@@ -1187,7 +1187,7 @@ radv_meta_image_to_image_cs(struct radv_cmd_buffer *cmd_buffer,
itoi_bind_descriptors(cmd_buffer, &src_view, &dst_view);
if (device->physical_device->rad_info.chip_class >= GFX9 &&
src->image->type == VK_IMAGE_TYPE_3D)
(src->image->type == VK_IMAGE_TYPE_3D || dst->image->type == VK_IMAGE_TYPE_3D))
pipeline = cmd_buffer->device->meta_state.itoi.pipeline_3d;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
......
src/amd/vulkan/radv_pipeline.c
View file @ ede874c1
......@@ -3295,8 +3295,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
(pipeline->graphics.prim_restart_enable &&
(device->physical_device->rad_info.family < CHIP_POLARIS10 ||
(prim != V_008958_DI_PT_POINTLIST &&
prim != V_008958_DI_PT_LINESTRIP &&
prim != V_008958_DI_PT_TRISTRIP))))
prim != V_008958_DI_PT_LINESTRIP))))
ia_multi_vgt_param.wd_switch_on_eop = true;
}
......
src/amd/vulkan/radv_private.h
View file @ ede874c1
......@@ -1433,6 +1433,14 @@ struct radv_image {
uint64_t clear_value_offset;
uint64_t dcc_pred_offset;
/*
* Metadata for the TC-compat zrange workaround. If the 32-bit value
* stored at this offset is UINT_MAX, the driver will emit
* DB_Z_INFO.ZRANGE_PRECISION=0, otherwise it will skip the
* SET_CONTEXT_REG packet.
*/
uint64_t tc_compat_zrange_offset;
/* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
VkDeviceMemory owned_memory;
};
......
src/amd/vulkan/radv_query.c
View file @ ede874c1
......@@ -1085,6 +1085,22 @@ void radv_CmdResetQueryPool(
}
}
static void emit_query_flush(struct radv_cmd_buffer *cmd_buffer,
struct radv_query_pool *pool)
{
if (cmd_buffer->pending_reset_query) {
if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
/* Only need to flush caches if the query pool size is
* large enough to be resetted using the compute shader
* path. Small pools don't need any cache flushes
* because we use a CP dma clear.
*/
si_emit_cache_flush(cmd_buffer);
cmd_buffer->pending_reset_query = false;
}
}
}
static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
uint64_t va,
VkQueryType query_type,
......@@ -1209,17 +1225,7 @@ void radv_CmdBeginQuery(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
if (cmd_buffer->pending_reset_query) {
if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
/* Only need to flush caches if the query pool size is
* large enough to be resetted using the compute shader
* path. Small pools don't need any cache flushes
* because we use a CP dma clear.
*/
si_emit_cache_flush(cmd_buffer);
cmd_buffer->pending_reset_query = false;
}
}
emit_query_flush(cmd_buffer, pool);
va += pool->stride * query;
......@@ -1280,6 +1286,8 @@ void radv_CmdWriteTimestamp(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo);
emit_query_flush(cmd_buffer, pool);
int num_queries = 1;
if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
num_queries = util_bitcount(cmd_buffer->state.subpass->view_mask);
......