Commits on Source (49)
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Juan A. Suarez Romero authored
Signed-off-by:Juan A. Suarez Romero <jasuarez@igalia.com>
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Sergii Romantsov authored
Test-case with depth-clear 0.5 and format MESA_FORMAT_Z24_UNORM_X8_UINT fails due inconsistent clear-value of 0.4999997. Maybe its better to improve? CC: Jason Ekstrand <jason.ekstrand@intel.com> Fixes: 0ae9ce0f (i965/clear: Quantize the depth clear value based on the format) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111113 Signed-off-by:
Sergii Romantsov <sergii.romantsov@globallogic.com> Signed-off-by:
Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net> (cherry picked from commit a86eccfb)
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Juan A. Suarez Romero authored
Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: -
Faith Ekstrand authored
There is an object-level preemption workaround which requires this. However, even without object-level preemption, we seem to have issues with geometry flickering when 3D and compute are combined in the same batch and this appears to fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109630 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111267 Cc: mesa-stable@lists.freedesktop.org Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit bc612536)
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Bas Nieuwenhuizen authored
Since it can introduce comparisons. Fixes: 028ce527 "radv: Add non-uniform indexing lowering." Reviewed-by:
Dave Airlie <airlied@redhat.com> Reviewed-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 2301b2e0)
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Bas Nieuwenhuizen authored
Fixes: 028ce527 "radv: Add non-uniform indexing lowering." Reviewed-by:
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Marek Olšák authored
Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org> Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (cherry picked from commit 6b3ee869) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by:
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Matt Turner authored
program_invocation_name and program_invocation_short_name are both GNU extensions. I don't believe one can exist without the other, so only check for program_invocation_name. Reviewed-by:
Eric Engestrom <eric.engestrom@intel.com> (cherry picked from commit c9b86cf5)
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Eric Engestrom authored
Fixes: 759b9403 ("util: Get program name based on path when possible") Signed-off-by:
Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 5b10ddf3)
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Erik Faye-Lund authored
Signed-off-by:
Erik Faye-Lund <erik.faye-lund@collabora.com> Fixes: a677799e ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding cap") Reviewed-by:
Marek Olšák <marek.olsak@amd.com> (cherry picked from commit 70a93922)
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Erik Faye-Lund authored
Signed-off-by:
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Bas Nieuwenhuizen authored
Mirroring radeonsi. CC: <mesa-stable@lists.freedesktop.org> Reviewed-by:
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Bas Nieuwenhuizen authored
CC: <mesa-stable@lists.freedesktop.org> Reviewed-by:
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Danylo Piliaiev authored
There is an object-level preemption workaround which requires this. However, even without object-level preemption, we seem to have issues with geometry flickering when 3D and compute are combined in the same batch and this appears to fix it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110395 Suggested-by:
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Val Packett authored
Fixes: 4201cc2d ("anv: Implement VK_KHX_external_semaphore_fd") Reviewed-by:
Emil Velikov <emil.velikov@collabora.com> Reviewed-by:
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Val Packett authored
Reviewed-by:
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Marek Olšák authored
This only appears to happen on Raven2. Possible way to reproduce: resource_get_handle(WINSYS_HANDLE_TYPE_KMS) --> sets is_shared = true resource_get_handle(WINSYS_HANDLE_TYPE_DMABUF) --> fail Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 8d0d753b)
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Juan A. Suarez Romero authored
Signed-off-by: -
Juan A. Suarez Romero authored
Signed-off-by: -
Juan A. Suarez Romero authored
Signed-off-by: -
Daniel Schürmann authored
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Ilia Mirkin authored
The compute paths in vl are a bit AMD-specific. For example, they (on nouveau), try to use a BGRX8 image format, which is not supported. Fixing all this is probably possible, but since the compute paths aren't in any way better, it's difficult to care. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213 Fixes: 9364d66c (gallium/auxiliary/vl: Add video compositor compute shader render) Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by:
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Danylo Piliaiev authored
Without loop_prepare_for_unroll loops are losing phis. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111411 Fixes: 5db98195 "nir: add loop unroll support for wrapper loops" Signed-off-by:
Timothy Arceri <tarceri@itsqueeze.com> (cherry picked from commit 84b3ef6a)
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Juan A. Suarez Romero authored
Signed-off-by: -
Juan A. Suarez Romero authored
Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: -
Kenneth Graunke authored
For renderable surfaces, we allocate SURFACE_STATEs for each bit in res->aux.possible_usages. Sampler views use res->aux.sampler_usages. When pinning buffers, we call surf_state_offset_for_aux() to calculate the offset to the desired surface state. surf_state_offset_for_aux() took an aux_modes parameter, which should be one of those two fields. However...it was not using that parameter. It always used the broader res->aux.possible_usages field directly. One of the callers, update_clear_value(), was passing incorrect masks for this parameter. It iterated through the bits in order, using u_bit_scan(), which destructively modifies the mask. So each time we called it, the count of bits before our selected mode was 0, which would cause us to always update the SURFACE_STATE for ISL_AUX_USAGE_NONE, rather than updating each in turn. This was hidden by the earlier bug where surf_state_offset_for_aux() ignored the parameter. Fixes: 7339660e ("iris: Add aux.sampler_usages.") Reviewed-by:
Rafael Antognolli <rafael.antognolli@intel.com> (cherry picked from commit 117a0368) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by:
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Juan A. Suarez Romero authored
Fixes: This commit does not apply cleanly on 19.1 branch, as it depends on other commits not present in the branch. Signed-off-by: -
Kenneth Graunke authored
This doesn't work for compressed formats, as the source texture and temporary texture would have different block sizes. (Forcing the driver to always take the GPU path would expose the bug.) Instead, just use the source format for the temporary, and let blorp_copy deal with overrides. The one case where we can't do this is ASTC, because isl won't let us create a linear ASTC surface. Fall back to the CPU paths there for now. Fixes: 9d1334d2 ("iris: Use copy_region and staging resources to avoid transfer stalls") Reviewed-by:
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Juan A. Suarez Romero authored
Fixes: The following commit depends on commits 77a1070d and df4c2ec5 in order to compile, which did not land in the branch. Signed-off-by:
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Tapani Pälli authored
Fixes errors seen with eglSetBlobCacheFuncsANDROID on Android when running dEQP that terminates and reinitializes a display. Fixes: 6f5b5709 "egl: add support for EGL_ANDROID_blob_cache" Signed-off-by:
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Kenneth Graunke authored
...by copying the implementation of anv_get_absolute_timeout(). Appears to fix a CTS test with 32-bit builds: GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush Fixes: f459c56b ("iris: Add fence support using drm_syncobj") Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Eric Engestrom <eric@engestrom.ch> (cherry picked from commit 7ee7b0ec)
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Andres Rodriguez authored
Make sure we read the updated data from the gpu in cases where WAIT_BIT is not set. Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit a410823b) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by:
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Jonas Ådahl authored
Whenever a buffer is allocated, e.g. by the first draw call or EGL call after a buffer swap, make sure the size is up to date. Prior to this commit, we failed to do so when querying the buffer age, or swapping buffers without any prior EGL call or draw call. Signed-off-by:
Jonas Ådahl <jadahl@gmail.com> Reviewed-by:
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Paulo Zanoni authored
Looks like a copy/paste error. This patch prevents a segfault when running the following on BDW: INTEL_DEBUG=no8,no16,do32 ./deqp-vk -n \ dEQP-VK.subgroups.arithmetic.compute.subgroupmin_dvec4 For the curious, the message we're getting is: CS compile failed: Failure to register allocate. Reduce number of live scalar values to avoid this. Fixes: 864737ce ("i965/fs: Build 32-wide compute shader when needed.") Reviewed-by:Paulo Zanoni <paulo.r.zanoni@intel.com> (cherry picked from commit 848d5e44) Signed-off-by:
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Marek Olšák authored
Cc: 19.2 19.1 <mesa-stable@lists.freedesktop.org> Reviewed-by:
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Kenneth Graunke authored
This always returns a int64_t, translating to _mesa_lroundevenf on systems where long is 64-bit, and llrintf where "long long" is needed. Fixes: 594fc0f8 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by:
Matt Turner <mattst88@gmail.com> (cherry picked from commit b59914e1)
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Kenneth Graunke authored
This fixes the following CTS test on 32-bit systems: GTF-GL46.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_init It does glGetTexImage of a 16-bit SNORM image, requesting 32-bit UNORM data. In get_tex_rgba_uncompressed, we round trip through float to handle image transfer ops for clamping. _mesa_format_convert does: _mesa_float_to_unorm(0.571428597f, 32) which translated to: _mesa_lroundevenf(0.571428597f * 0xffffffffu) which produced different results on 64-bit and 32-bit systems: 64-bit: result = 0x92492500 32-bit: result = 0x80000000 This is because the size of "long" varies between the two systems, and 0x92492500 is too large to fit in a signed 32-bit integer. To fix this, we switch to the new _mesa_i64roundevenf function which always does the 64-bit operation. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104395 Fixes: 594fc0f8 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().") Reviewed-by:
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Kenneth Graunke authored
src0 vstride and type overlap with bits of the extended descriptor. brw_set_desc() also sets the extended descriptor to 0. So by setting the descriptor, then setting src0, we were accidentally setting a bunch of extended descriptor bits unintentionally. When using this infrastructure for framebuffer writes (in a future patch), this ended up setting the extended descriptor bit 20, which is "Null Render Target" on Icelake, causing nothing to be written to the framebuffer. Reviewed-by:
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Ian Romanick authored
This caused a problem on Sandybridge where an open-coded bitfieldReverse() function could be optimized to a nir_op_bitfield_reverse that would generate an unsupported BFREV instruction in the backend. This was encountered in some Unreal4 tech demos in shader-db. The bug was not previously noticed because we don't actually try to run those demos on Sandybridge. The fixes tag is a bit a lie. The actual bug was introduced about 26,000 commits earlier in 371c4b3c ("nir: Recognize open-coded bitfield_reverse."). Without the NIR lowering pass, the flag needed to avoid the optimization does not exist. Hopefully nobody will care to fix this on an earlier Mesa release. Reviewed-by:
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Ian Romanick authored
See the previous commit for the explanation of the Fixes tag. Hurts 21 shaders in shader-db. All of the hurt shaders are in Unreal Engine 4 tech demos. Reviewed-by:
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Pierre-Eric Pelloux-Prayer authored
This fixes a hang in shadertoy for radeonsi where a buffer was initialized with: value -= value with value being undefined. In this case LLVM replace the operation with an assignment to NaN. Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111241 Reviewed-by:
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Juan A. Suarez Romero authored
Signed-off-by: -
Juan A. Suarez Romero authored
Signed-off-by: -
Timo Aaltonen authored
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Timo Aaltonen authored
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Timo Aaltonen authored
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Timo Aaltonen authored
mesa-19.1.6
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Timo Aaltonen authored
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Timo Aaltonen authored
