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Commits on Source (44)
......@@ -66,8 +66,33 @@ f9e8456c39136aa41f85f82758a00e5aa2aab334
a4a104fc81e93555899050efac23c3cd6ba762ab
24ee53231da84a1be5ec08abebe8a2ff6aa019ca
4c43ec461de4f122d5d6566361d064c816e4ef69
743e11c10b180247488ae0cc24900560e0a74e2b
4ffb575da59fd3aece02734ca4fd3212d5002d55
8c048af5890d43578ca41eb9dcfa60cb9cc3fc9c
c92a463d2341dd7893dd8b54775930ed9be72ac0
# These have more than one fixes tag and generate a warning
#
24839663a40257e0468406d72c48d431b5ae2bd4
6ff1c479968819b93c46d24bd898e89ce14ac401
ac0856ae4100a05dcd1fd932d9fd10200f8f7a7c
c9f54486959716762e6818dabb0a73a8cd46df67
# This patch requires patches that would require python 3, the thing they're
# fixing isn't really even a bug, it's more of a style choice, so I'm not going
# to pull them.
#
48820ed8da0ad50d51a58f26e156d82b685492e2
# This patch doesn't apply and either needs to be backported or can just be
# ignored
#
1e40f6948310be07abb2d0198e6602769892cdac
# This patch isn't necessary, since the patch it fixes is not present in 18.1
#
a72dbc461bdb7714656e62cd8f4b00a404c2e6e0
# This requires a much more significant patch not present in 18.1
#
4dc244eb447b1fa4e39d67a58328ed774395c901
mesa (18.1.8-1) unstable; urgency=medium
* New upstream release.
-- Timo Aaltonen <tjaalton@debian.org> Mon, 10 Sep 2018 10:34:39 +0300
mesa (18.1.7-1) unstable; urgency=medium
* New upstream release.
......
......@@ -75,7 +75,7 @@ you think you've spotted a bug let developers know by filing a
Version 2.6.4 or later should work.
</li>
<li><a href="http://www.makotemplates.org/">Python Mako module</a> -
Python Mako module is required. Version 0.3.4 or later should work.
Python Mako module is required. Version 0.8.0 or later should work.
</li>
<li>lex / yacc - for building the Mesa IR and GLSL compiler.
<div>
......
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
0c3c240bcd1352d179e65993214f9d55a399beac852c3ab4433e8df9b6c51c83 mesa-18.1.7.tar.gz
655e3b32ce3bdddd5e6e8768596e5d4bdef82d0dd37067c324cc4b2daa207306 mesa-18.1.7.tar.xz
</pre>
......
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.1.8 Release Notes / September 7 2018</h1>
<p>
Mesa 18.1.8 is a bug fix release which fixes bugs found since the 18.1.7 release.
</p>
<p>
Mesa 18.1.8 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93355">Bug 93355</a> - [BXT,SKLGT4e] intermittent ext_framebuffer_multisample.accuracy fails</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=101247">Bug 101247</a> - Mesa fails to link GLSL programs with unused output blocks</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104809">Bug 104809</a> - anv: DOOM 2016 and Wolfenstein II:The New Colossus crash due to not having depthBoundsTest</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=105904">Bug 105904</a> - Needed to delete mesa shader cache after driver upgrade for 32 bit wine vulkan programs to work.</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106738">Bug 106738</a> - No test for miptrees with DRI modifiers</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=106865">Bug 106865</a> - [GLK] piglit.spec.ext_framebuffer_multisample.accuracy stencil tests fail</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107359">Bug 107359</a> - [Regression] [bisected] [OpenGL CTS] [SKL,BDW] KHR-GL46.texture_barrier*-texels, GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners, and GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners fail with some configuration</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107477">Bug 107477</a> - [DXVK] Setting high shader quality in GTA V results in LLVM error</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107579">Bug 107579</a> - [SNB] The graphic corruption when we reuse the GS compiled and used for TFB when statebuffer contain magic trash in the unused space</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107601">Bug 107601</a> - Rise of the Tomb Raider Segmentation Fault when the game starts</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=107760">Bug 107760</a> - GPU Hang when Playing DiRT 3 Complete Edition using Steam Play with DXVK</li>
</ul>
<h2>Changes</h2>
<p>Andrii Simiklit (1):</p>
<ul>
<li>i965/gen6/xfb: handle case where transform feedback is not active</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Add missing checks in radv_get_image_format_properties.</li>
<li>radv: Fix CMASK dimensions.</li>
<li>radv: Use a lower max offchip buffer count.</li>
</ul>
<p>Christian Gmeiner (1):</p>
<ul>
<li>tegra: fix memory leak</li>
</ul>
<p>Daniel Stone (1):</p>
<ul>
<li>st/dri: Don't expose sRGB formats to clients</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>ac/radeonsi: fix CIK copy max size</li>
</ul>
<p>Dylan Baker (10):</p>
<ul>
<li>docs: Add mesa 18.1.7 notes</li>
<li>cherry-ignore: add a patch</li>
<li>cherry-ignore: Add more 18.2 only patches</li>
<li>meson: Actually load translation files</li>
<li>cherry-ignore: Add more 18.2 patches</li>
<li>cherry-ignore: Add additional patch</li>
<li>cherry-ignore: Add patch that doesn't apply to 18.1</li>
<li>cherry-ignore: Add a couple of two fixes warning patches</li>
<li>cherry-ignore: Add patch that needs more significant patches to function</li>
<li>Bump version to 18.1.8</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>docs: update required mako version</li>
</ul>
<p>Grazvydas Ignotas (1):</p>
<ul>
<li>radv: place pointer length into cache uuid</li>
</ul>
<p>Gurchetan Singh (2):</p>
<ul>
<li>meson: fix egl build for surfaceless</li>
<li>meson: fix egl build for android</li>
</ul>
<p>Ian Romanick (2):</p>
<ul>
<li>i965/vec4: Clamp indirect tes input array reads with 0x0fffffff</li>
<li>i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset</li>
</ul>
<p>Jason Ekstrand (5):</p>
<ul>
<li>anv: Fill holes in the VF VUE to zero</li>
<li>nir/algebraic: Be more careful converting ushr to extract_u8/16</li>
<li>egl/dri2: Add a helper for the number of planes for a FOURCC format</li>
<li>egl/dri2: Guard against invalid fourcc formats</li>
<li>anv/blorp: Do more flushing around HiZ clears</li>
</ul>
<p>Juan A. Suarez Romero (1):</p>
<ul>
<li>egl/wayland: do not leak wl_buffer when it is locked</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv: blorp: support multiple aspect blits</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>glapi: actually implement GL_EXT_robustness for GLES</li>
</ul>
<p>Nanley Chery (7):</p>
<ul>
<li>intel/isl: Avoid tiling some 16K-wide render targets</li>
<li>i965: Make blt_pitch public</li>
<li>i965/miptree: Drop an if case from retile_as_linear</li>
<li>i965/miptree: Use the correct BLT pitch</li>
<li>i965/miptree: Use miptree_map in map_blit functions</li>
<li>i965/miptree: Fix can_blit_slice()</li>
<li>i965/gen7_urb: Re-emit PUSH_CONSTANT_ALLOC on some gen9</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: fix passing clip/cull distances from VS to PS</li>
</ul>
<p>vadym.shovkoplias (1):</p>
<ul>
<li>glsl/linker: Allow unused in blocks which are not declated on previous stage</li>
</ul>
</div>
</body>
</html>
......@@ -9123,7 +9123,9 @@
#define CIK_SDMA_PACKET_SEMAPHORE 0x7
#define CIK_SDMA_PACKET_CONSTANT_FILL 0xb
#define CIK_SDMA_PACKET_SRBM_WRITE 0xe
#define CIK_SDMA_COPY_MAX_SIZE 0x3fffe0
/* There is apparently an undocumented HW "feature" that
prevents the HW from copying past 256 bytes of (1 << 22) */
#define CIK_SDMA_COPY_MAX_SIZE 0x3fff00
 
enum amd_cmp_class_flags {
S_NAN = 1 << 0, // Signaling NaN
......
......@@ -60,7 +60,7 @@ radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
memcpy(uuid, &mesa_timestamp, 4);
memcpy((char*)uuid + 4, &llvm_timestamp, 4);
memcpy((char*)uuid + 8, &f, 2);
snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void *));
return 0;
}
......@@ -1860,10 +1860,30 @@ radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buff
device->physical_device->rad_info.family != CHIP_CARRIZO &&
device->physical_device->rad_info.family != CHIP_STONEY;
unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
unsigned max_offchip_buffers = max_offchip_buffers_per_se *
device->physical_device->rad_info.max_se;
unsigned max_offchip_buffers;
unsigned offchip_granularity;
unsigned hs_offchip_param;
/*
* Per RadeonSI:
* This must be one less than the maximum number due to a hw limitation.
* Various hardware bugs in SI, CIK, and GFX9 need this.
*
* Per AMDVLK:
* Vega10 should limit max_offchip_buffers to 508 (4 * 127).
* Gfx7 should limit max_offchip_buffers to 508
* Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
*
* Follow AMDVLK here.
*/
if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
device->physical_device->rad_info.chip_class == CIK ||
device->physical_device->rad_info.chip_class == SI)
--max_offchip_buffers_per_se;
max_offchip_buffers = max_offchip_buffers_per_se *
device->physical_device->rad_info.max_se;
switch (device->tess_offchip_block_dw_size) {
default:
assert(0);
......
......@@ -1180,6 +1180,25 @@ static VkResult radv_get_image_format_properties(struct radv_physical_device *ph
}
}
if (info->usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_TRANSFER_SRC_BIT)) {
goto unsupported;
}
}
if (info->usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_TRANSFER_DST_BIT)) {
goto unsupported;
}
}
if (info->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
if (!(format_feature_flags & (VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT))) {
goto unsupported;
}
}
*pImageFormatProperties = (VkImageFormatProperties) {
.maxExtent = maxExtent,
.maxMipLevels = maxMipLevels,
......
......@@ -830,8 +830,8 @@ radv_image_get_cmask_info(struct radv_device *device,
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned width = align(image->info.width, cl_width*8);
unsigned height = align(image->info.height, cl_height*8);
unsigned width = align(image->surface.u.legacy.level[0].nblk_x, cl_width*8);
unsigned height = align(image->surface.u.legacy.level[0].nblk_y, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
/* Each element of CMASK is a nibble. */
......
......@@ -1944,9 +1944,10 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
int idx = variable->data.location;
unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
LLVMValueRef interp;
uint64_t mask;
variable->data.driver_location = idx * 4;
ctx->input_mask |= ((1ull << attrib_count) - 1) << variable->data.location;
mask = ((1ull << attrib_count) - 1) << variable->data.location;
if (glsl_get_base_type(glsl_without_array(variable->type)) == GLSL_TYPE_FLOAT) {
unsigned interp_type;
......@@ -1964,6 +1965,15 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
for (unsigned i = 0; i < attrib_count; ++i)
ctx->inputs[ac_llvm_reg_index_soa(idx + i, 0)] = interp;
if (idx == VARYING_SLOT_CLIP_DIST0) {
/* Do not account for the number of components inside the array
* of clip/cull distances because this might wrongly set other
* bits like primitive ID or layer.
*/
mask = 1ull << VARYING_SLOT_CLIP_DIST0;
}
ctx->input_mask |= mask;
}
static void
......@@ -2028,6 +2038,17 @@ handle_fs_inputs(struct radv_shader_context *ctx,
if (!interp_param)
ctx->shader_info->fs.flat_shaded_mask |= 1u << index;
++index;
} else if (i == VARYING_SLOT_CLIP_DIST0) {
int length = ctx->shader_info->info.ps.num_input_clips_culls;
for (unsigned j = 0; j < length; j += 4) {
inputs = ctx->inputs + ac_llvm_reg_index_soa(i, j);
interp_param = *inputs;
interp_fs_input(ctx, index, interp_param,
ctx->abi.prim_mask, inputs);
++index;
}
} else if (i == VARYING_SLOT_POS) {
for(int i = 0; i < 3; ++i)
inputs[i] = ctx->abi.frag_pos[i];
......@@ -2295,6 +2316,13 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
&args, sizeof(args));
/* Export the clip/cull distances values to the next stage. */
radv_export_param(ctx, param_count, &slots[0], 0xf);
outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0] = param_count++;
if (ctx->num_output_clips + ctx->num_output_culls > 4) {
radv_export_param(ctx, param_count, &slots[4], 0xf);
outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1] = param_count++;
}
}
LLVMValueRef pos_values[4] = {ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_0, ctx->ac.f32_1};
......
......@@ -3050,6 +3050,23 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
ps_offset++;
}
if (ps->info.info.ps.num_input_clips_culls) {
unsigned vs_offset;
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
++ps_offset;
}
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
ps->info.info.ps.num_input_clips_culls > 4) {
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
++ps_offset;
}
}
for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
......
......@@ -171,6 +171,7 @@ struct radv_shader_info {
bool has_pcoord;
bool prim_id_input;
bool layer_input;
uint8_t num_input_clips_culls;
} ps;
struct {
bool uses_grid_size;
......
......@@ -293,6 +293,7 @@ static void
gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
struct radv_shader_info *info)
{
unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
const struct glsl_type *type = glsl_without_array(var->type);
int idx = var->data.location;
......@@ -306,6 +307,9 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
case VARYING_SLOT_LAYER:
info->ps.layer_input = true;
break;
case VARYING_SLOT_CLIP_DIST0:
info->ps.num_input_clips_culls = attrib_count;
break;
default:
break;
}
......
......@@ -667,8 +667,8 @@ public:
* variable has been used. For example, it is an error to redeclare a
* variable as invariant after it has been used.
*
* This is only maintained in the ast_to_hir.cpp path, not in
* Mesa's fixed function or ARB program paths.
* This is maintained in the ast_to_hir.cpp path and during linking,
* but not in Mesa's fixed function or ARB program paths.
*/
unsigned used:1;
......
......@@ -417,9 +417,15 @@ validate_interstage_inout_blocks(struct gl_shader_program *prog,
* write to any of the pre-defined outputs (e.g. if the vertex shader
* does not write to gl_Position, etc), which is allowed and results in
* undefined behavior.
*
* From Section 4.3.4 (Inputs) of the GLSL 1.50 spec:
*
* "Only the input variables that are actually read need to be written
* by the previous stage; it is allowed to have superfluous
* declarations of input variables."
*/
if (producer_def == NULL &&
!is_builtin_gl_in_block(var, consumer->Stage)) {
!is_builtin_gl_in_block(var, consumer->Stage) && var->data.used) {
linker_error(prog, "Input block `%s' is not an output of "
"the previous stage\n", var->get_interface_type()->name);
return;
......
......@@ -427,13 +427,13 @@ optimizations = [
('unpack_64_2x32_split_y', a)), a),
# Byte extraction
(('ushr', a, 24), ('extract_u8', a, 3), '!options->lower_extract_byte'),
(('ushr', 'a@32', 24), ('extract_u8', a, 3), '!options->lower_extract_byte'),
(('iand', 0xff, ('ushr', a, 16)), ('extract_u8', a, 2), '!options->lower_extract_byte'),
(('iand', 0xff, ('ushr', a, 8)), ('extract_u8', a, 1), '!options->lower_extract_byte'),
(('iand', 0xff, a), ('extract_u8', a, 0), '!options->lower_extract_byte'),
# Word extraction
(('ushr', a, 16), ('extract_u16', a, 1), '!options->lower_extract_word'),
(('ushr', 'a@32', 16), ('extract_u16', a, 1), '!options->lower_extract_word'),
(('iand', 0xffff, a), ('extract_u16', a, 0), '!options->lower_extract_word'),
# Subtracts
......
......@@ -2223,13 +2223,13 @@ dri2_check_dma_buf_attribs(const _EGLImageAttribs *attrs)
return EGL_TRUE;
}
/* Returns the total number of file descriptors. Zero indicates an error. */
/* Returns the total number of planes for the format or zero if it isn't a
* valid fourcc format.
*/
static unsigned
dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
dri2_num_fourcc_format_planes(EGLint format)
{
unsigned plane_n;
switch (attrs->DMABufFourCC.Value) {
switch (format) {
case DRM_FORMAT_R8:
case DRM_FORMAT_RG88:
case DRM_FORMAT_GR88:
......@@ -2277,14 +2277,14 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
case DRM_FORMAT_YVYU:
case DRM_FORMAT_UYVY:
case DRM_FORMAT_VYUY:
plane_n = 1;
break;
return 1;
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV21:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV61:
plane_n = 2;
break;
return 2;
case DRM_FORMAT_YUV410:
case DRM_FORMAT_YVU410:
case DRM_FORMAT_YUV411:
......@@ -2295,9 +2295,19 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
case DRM_FORMAT_YVU422:
case DRM_FORMAT_YUV444:
case DRM_FORMAT_YVU444:
plane_n = 3;
break;
return 3;
default:
return 0;
}
}
/* Returns the total number of file descriptors. Zero indicates an error. */
static unsigned
dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
{
unsigned plane_n = dri2_num_fourcc_format_planes(attrs->DMABufFourCC.Value);
if (plane_n == 0) {
_eglError(EGL_BAD_ATTRIBUTE, "invalid format");
return 0;
}
......@@ -2371,6 +2381,18 @@ dri2_query_dma_buf_formats(_EGLDriver *drv, _EGLDisplay *disp,
formats, count))
return EGL_FALSE;
if (max > 0) {
/* Assert that all of the formats returned are actually fourcc formats.
* Some day, if we want the internal interface function to be able to
* return the fake fourcc formats defined in dri_interface.h, we'll have
* to do something more clever here to pair the list down to just real
* fourcc formats so that we don't leak the fake internal ones.
*/
for (int i = 0; i < *count; i++) {
assert(dri2_num_fourcc_format_planes(formats[i]) > 0);
}
}
return EGL_TRUE;
}
......@@ -2381,6 +2403,9 @@ dri2_query_dma_buf_modifiers(_EGLDriver *drv, _EGLDisplay *disp, EGLint format,
{
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
if (dri2_num_fourcc_format_planes(format) == 0)
return _eglError(EGL_BAD_PARAMETER, "invalid fourcc format");
if (max < 0)
return _eglError(EGL_BAD_PARAMETER, "invalid value for max count of formats");
......
......@@ -292,6 +292,7 @@ struct dri2_egl_surface
struct {
#ifdef HAVE_WAYLAND_PLATFORM
struct wl_buffer *wl_buffer;
bool wl_release;
__DRIimage *dri_image;
/* for is_different_gpu case. NULL else */
__DRIimage *linear_copy;
......
......@@ -179,9 +179,12 @@ wl_buffer_release(void *data, struct wl_buffer *buffer)
if (dri2_surf->color_buffers[i].wl_buffer == buffer)
break;
if (i == ARRAY_SIZE(dri2_surf->color_buffers)) {
assert (i < ARRAY_SIZE(dri2_surf->color_buffers));
if (dri2_surf->color_buffers[i].wl_release) {
wl_buffer_destroy(buffer);
return;
dri2_surf->color_buffers[i].wl_release = false;
dri2_surf->color_buffers[i].wl_buffer = NULL;
}
dri2_surf->color_buffers[i].locked = false;
......@@ -417,9 +420,14 @@ dri2_wl_release_buffers(struct dri2_egl_surface *dri2_surf)
dri2_egl_display(dri2_surf->base.Resource.Display);
for (int i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
if (dri2_surf->color_buffers[i].wl_buffer &&
!dri2_surf->color_buffers[i].locked)
if (dri2_surf->color_buffers[i].wl_buffer) {
if (dri2_surf->color_buffers[i].locked) {
dri2_surf->color_buffers[i].wl_release = true;
} else {
wl_buffer_destroy(dri2_surf->color_buffers[i].wl_buffer);
dri2_surf->color_buffers[i].wl_buffer = NULL;
}
}
if (dri2_surf->color_buffers[i].dri_image)
dri2_dpy->image->destroyImage(dri2_surf->color_buffers[i].dri_image);
if (dri2_surf->color_buffers[i].linear_copy)
......@@ -428,11 +436,9 @@ dri2_wl_release_buffers(struct dri2_egl_surface *dri2_surf)
munmap(dri2_surf->color_buffers[i].data,
dri2_surf->color_buffers[i].data_size);
dri2_surf->color_buffers[i].wl_buffer = NULL;
dri2_surf->color_buffers[i].dri_image = NULL;
dri2_surf->color_buffers[i].linear_copy = NULL;
dri2_surf->color_buffers[i].data = NULL;
dri2_surf->color_buffers[i].locked = false;
}
if (dri2_dpy->dri2)
......@@ -961,6 +967,8 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
dri2_surf->current->wl_buffer =
create_wl_buffer(dri2_dpy, dri2_surf, image);
dri2_surf->current->wl_release = false;
wl_buffer_add_listener(dri2_surf->current->wl_buffer,
&wl_buffer_listener, dri2_surf);
}
......