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bin/.cherry-ignore
View file @ b1517248
......@@ -2,3 +2,15 @@
c02390f8fcd367c7350db568feabb2f062efca14 egl/wayland: rather obvious build fix
# fixes: The commit addresses b4476138d5ad3f8d30c14ee61f2f375edfdbab2a
ff6f1dd0d3c6b4c15ca51b478b2884d14f6a1e06 meson: libfreedreno depends upon libdrm (for fence support)
# fixes: This commit requires commits aeaf8dbd097 and 7484bc894b9 which did not
# land in branch.
f67dea5e19ef14187be0e8d0f61b1f764c7ccb4f radv: Fix multiview depth clears
# stable The commits aren't suitable in their present form.
bfe31c5e461a1330d6f606bf5310685eff1198dd nir/builder: Add nir_i2i and nir_u2u helpers which take a bit size
abfe674c54bee6f8fdcae411b07db89c10b9d530 spirv: Handle arbitrary bit sizes for deref array indices
# warn The commits refer stale sha, yet don't fix anything in particular.
98984b7cdd79c15cc7331c791f8be61e873b8bbd Revert "mapi/new: sort by slot number"
9f86f1da7c68b5b900cd6f60925610ff1225a72d egl: add glvnd entrypoints for EGL_MESA_query_driver
bin/get-pick-list.sh
View file @ b1517248
......@@ -44,7 +44,7 @@ is_sha_nomination()
# Treat only the current line
id=`echo "$fixes" | tail -n $fixes_count | head -n 1 | cut -d : -f 2`
fixes_count=$(($fixes_count-1))
if ! git show $id &>/dev/null; then
if ! git show $id >/dev/null 2>&1; then
echo WARNING: Commit $1 lists invalid sha $id
fi
done
......@@ -143,7 +143,7 @@ do
esac
printf "[ %8s ] " "$tag"
git --no-pager show --summary --oneline $sha
git --no-pager show --no-patch --oneline $sha
done
rm -f already_picked
......
configure.ac
View file @ b1517248
......@@ -1864,6 +1864,7 @@ for plat in $platforms; do
;;
drm)
test "x$enable_egl" = "xyes" &&
test "x$enable_gbm" = "xno" &&
AC_MSG_ERROR([EGL platform drm needs gbm])
DEFINES="$DEFINES -DHAVE_DRM_PLATFORM"
......
debian/changelog
View file @ b1517248
mesa (18.3.2-2) UNRELEASED; urgency=medium
mesa (18.3.3-1) unstable; urgency=medium
[ James Clarke ]
* Add pkg.mesa.nolibva build profile; this breaks the mesa -> libva-dev ->
libva-glx1 -> libgl1-mesa-glx dependency loop when bootstrapping.
(Closes: #870434)
-- James Clarke <jrtc27@debian.org> Thu, 17 Jan 2019 22:10:22 +0000
[ Timo Aaltonen ]
* New upstream release.
-- Timo Aaltonen <tjaalton@debian.org> Wed, 06 Feb 2019 11:36:46 +0200
mesa (18.3.2-1) unstable; urgency=medium
......
docs/relnotes/18.3.2.html
View file @ b1517248
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
1cde4fafd40cd1ad4ee3a13b364b7a0175a08b7afdd127fb46f918c1e1dfd4b0 mesa-18.3.2.tar.gz
f7ce7181c07b6d8e0132da879af1729523a6c8aa87f79a9d59dfd064024cfb35 mesa-18.3.2.tar.xz
</pre>
......
docs/relnotes/18.3.3.html 0 → 100644
View file @ b1517248
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 18.3.3 Release Notes / January 31, 2019</h1>
<p>
Mesa 18.3.3 is a bug fix release which fixes bugs found since the 18.3.2 release.
</p>
<p>
Mesa 18.3.3 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108877">Bug 108877</a> - OpenGL CTS gl43 test cases were interrupted due to segment fault</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109023">Bug 109023</a> - error: inlining failed in call to always_inline ‘__m512 _mm512_and_ps(__m512, __m512)’: target specific option mismatch</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109129">Bug 109129</a> - format_types.h:1220: undefined reference to `_mm256_cvtps_ph'</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109229">Bug 109229</a> - glLinkProgram locks up for ~30 seconds</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109242">Bug 109242</a> - [RADV] The Witcher 3 system freeze</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109488">Bug 109488</a> - Mesa 18.3.2 crash on a specific fragment shader (assert triggered) / already fixed on the master branch.</li>
</ul>
<h2>Changes</h2>
<p>Andres Gomez (2):</p>
<ul>
<li>bin/get-pick-list.sh: fix the oneline printing</li>
<li>bin/get-pick-list.sh: fix redirection in sh</li>
</ul>
<p>Axel Davy (1):</p>
<ul>
<li>st/nine: Immediately upload user provided textures</li>
</ul>
<p>Bas Nieuwenhuizen (3):</p>
<ul>
<li>radv: Only use 32 KiB per threadgroup on Stoney.</li>
<li>radv: Set partial_vs_wave for pipelines with just GS, not tess.</li>
<li>nir: Account for atomics in copy propagation.</li>
</ul>
<p>Bruce Cherniak (1):</p>
<ul>
<li>gallium/swr: Fix multi-context sync fence deadlock.</li>
</ul>
<p>Carsten Haitzler (Rasterman) (2):</p>
<ul>
<li>vc4: Use named parameters for the NEON inline asm.</li>
<li>vc4: Declare the cpu pointers as being modified in NEON asm.</li>
</ul>
<p>Danylo Piliaiev (1):</p>
<ul>
<li>glsl: Fix copying function's out to temp if dereferenced by array</li>
</ul>
<p>Dave Airlie (3):</p>
<ul>
<li>dri_interface: add put shm image2 (v2)</li>
<li>glx: add support for putimageshm2 path (v2)</li>
<li>gallium: use put image shm2 path (v2)</li>
</ul>
<p>Dylan Baker (4):</p>
<ul>
<li>meson: allow building dri driver without window system if osmesa is classic</li>
<li>meson: fix swr KNL build</li>
<li>meson: Fix compiler checks for SWR with ICC</li>
<li>meson: Add warnings and errors when using ICC</li>
</ul>
<p>Emil Velikov (4):</p>
<ul>
<li>docs: add sha256 checksums for 18.3.2</li>
<li>cherry-ignore: radv: Fix multiview depth clears</li>
<li>cherry-ignore: spirv: Handle arbitrary bit sizes for deref array indices</li>
<li>cherry-ignore: WARNING: Commit XXX lists invalid sha</li>
</ul>
<p>Eric Anholt (2):</p>
<ul>
<li>vc4: Don't leak the GPU fd for renderonly usage.</li>
<li>vc4: Enable NEON asm on meson cross-builds.</li>
</ul>
<p>Eric Engestrom (2):</p>
<ul>
<li>configure: EGL requirements only apply if EGL is built</li>
<li>meson/vdpau: add missing soversion</li>
</ul>
<p>Iago Toral Quiroga (1):</p>
<ul>
<li>anv/device: fix maximum number of images supported</li>
</ul>
<p>Jason Ekstrand (3):</p>
<ul>
<li>anv/nir: Rework arguments to apply_pipeline_layout</li>
<li>anv: Only parse pImmutableSamplers if the descriptor has samplers</li>
<li>nir/xfb: Fix offset accounting for dvec3/4</li>
</ul>
<p>Karol Herbst (2):</p>
<ul>
<li>nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions</li>
<li>glsl/lower_output_reads: set invariant and precise flags on temporaries</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>anv: fix invalid binding table index computation</li>
</ul>
<p>Marek Olšák (4):</p>
<ul>
<li>radeonsi: also apply the GS hang workaround to draws without tessellation</li>
<li>radeonsi: fix a u_blitter crash after a shader with FBFETCH</li>
<li>radeonsi: fix rendering to tiny viewports where the viewport center is &gt; 8K</li>
<li>st/mesa: purge framebuffers when unbinding a context</li>
</ul>
<p>Niklas Haas (1):</p>
<ul>
<li>radv: correctly use vulkan 1.0 by default</li>
</ul>
<p>Pierre Moreau (1):</p>
<ul>
<li>meson: Fix with_gallium_icd to with_opencl_icd</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>loader: fix the no-modifiers case</li>
</ul>
<p>Samuel Pitoiset (1):</p>
<ul>
<li>radv: clean up setting partial_es_wave for distributed tess on VI</li>
</ul>
<p>Timothy Arceri (5):</p>
<ul>
<li>ac/nir_to_llvm: fix interpolateAt* for arrays</li>
<li>ac/nir_to_llvm: fix clamp shadow reference for more hardware</li>
<li>radv/ac: fix some fp16 handling</li>
<li>glsl: use remap location when serialising uniform program resource data</li>
<li>glsl: Copy function out to temp if we don't directly ref a variable</li>
</ul>
<p>Tomeu Vizoso (1):</p>
<ul>
<li>etnaviv: Consolidate buffer references from framebuffers</li>
</ul>
<p>Vinson Lee (1):</p>
<ul>
<li>meson: Fix typo.</li>
</ul>
</div>
</body>
</html>
include/GL/internal/dri_interface.h
View file @ b1517248
......@@ -589,7 +589,7 @@ struct __DRIdamageExtensionRec {
* SWRast Loader extension.
*/
#define __DRI_SWRAST_LOADER "DRI_SWRastLoader"
#define __DRI_SWRAST_LOADER_VERSION 4
#define __DRI_SWRAST_LOADER_VERSION 5
struct __DRIswrastLoaderExtensionRec {
__DRIextension base;
......@@ -649,6 +649,23 @@ struct __DRIswrastLoaderExtensionRec {
void (*getImageShm)(__DRIdrawable *readable,
int x, int y, int width, int height,
int shmid, void *loaderPrivate);
/**
* Put shm image to drawable (v2)
*
* The original version fixes srcx/y to 0, and expected
* the offset to be adjusted. This version allows src x,y
* to not be included in the offset. This is needed to
* avoid certain overflow checks in the X server, that
* result in lost rendering.
*
* \since 5
*/
void (*putImageShm2)(__DRIdrawable *drawable, int op,
int x, int y,
int width, int height, int stride,
int shmid, char *shmaddr, unsigned offset,
void *loaderPrivate);
};
/**
......
meson.build
View file @ b1517248
# Copyright © 2017-2018 Intel Corporation
# Copyright © 2017-2019 Intel Corporation
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal
......@@ -165,6 +165,14 @@ with_gallium_svga = _drivers.contains('svga')
with_gallium_virgl = _drivers.contains('virgl')
with_gallium_swr = _drivers.contains('swr')
if cc.get_id() == 'intel'
if meson.version().version_compare('< 0.49.0')
error('Meson does not have sufficient support of ICC before 0.49.0 to compile mesa')
elif with_gallium_swr and meson.version().version_compare('== 0.49.0')
warning('Meson as of 0.49.0 is sufficient for compiling mesa with ICC, but there are some caveats with SWR. 0.49.1 should resolve all of these')
endif
endif
with_gallium = _drivers.length() != 0 and _drivers != ['']
if with_gallium and system_has_kms_drm
......@@ -385,8 +393,8 @@ if with_any_vk and (with_platform_x11 and not with_dri3)
error('Vulkan drivers require dri3 for X11 support')
endif
if with_dri
if with_glx == 'disabled' and not with_egl and not with_gbm
error('building dri drivers require at least one windowing system')
if with_glx == 'disabled' and not with_egl and not with_gbm and with_osmesa != 'classic'
error('building dri drivers require at least one windowing system or classic osmesa')
endif
endif
......@@ -671,7 +679,7 @@ if _opencl != 'disabled'
else
dep_clc = null_dep
with_gallium_opencl = false
with_gallium_icd = false
with_opencl_icd = false
endif
gl_pkgconfig_c_flags = []
......
src/amd/common/ac_nir_to_llvm.c
View file @ b1517248
......@@ -2802,15 +2802,16 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
LLVMValueRef result[4];
LLVMValueRef interp_param, attr_number;
LLVMValueRef interp_param;
unsigned location;
unsigned chan;
LLVMValueRef src_c0 = NULL;
LLVMValueRef src_c1 = NULL;
LLVMValueRef src0 = NULL;
nir_variable *var = nir_deref_instr_get_variable(nir_instr_as_deref(instr->src[0].ssa->parent_instr));
int input_index = ctx->abi->fs_input_attr_indices[var->data.location - VARYING_SLOT_VAR0];
nir_deref_instr *deref_instr = nir_instr_as_deref(instr->src[0].ssa->parent_instr);
nir_variable *var = nir_deref_instr_get_variable(deref_instr);
int input_base = ctx->abi->fs_input_attr_indices[var->data.location - VARYING_SLOT_VAR0];
switch (instr->intrinsic) {
case nir_intrinsic_interp_deref_at_centroid:
location = INTERP_CENTROID;
......@@ -2840,7 +2841,6 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
src_c1 = LLVMBuildFSub(ctx->ac.builder, src_c1, halfval, "");
}
interp_param = ctx->abi->lookup_interp_param(ctx->abi, var->data.interpolation, location);
attr_number = LLVMConstInt(ctx->ac.i32, input_index, false);
if (location == INTERP_CENTER) {
LLVMValueRef ij_out[2];
......@@ -2878,9 +2878,44 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
}
LLVMValueRef array_idx = ctx->ac.i32_0;
while(deref_instr->deref_type != nir_deref_type_var) {
if (deref_instr->deref_type == nir_deref_type_array) {
unsigned array_size = glsl_get_aoa_size(deref_instr->type);
if (!array_size)
array_size = 1;
LLVMValueRef offset;
nir_const_value *const_value = nir_src_as_const_value(deref_instr->arr.index);
if (const_value) {
offset = LLVMConstInt(ctx->ac.i32, array_size * const_value->u32[0], false);
} else {
LLVMValueRef indirect = get_src(ctx, deref_instr->arr.index);
offset = LLVMBuildMul(ctx->ac.builder, indirect,
LLVMConstInt(ctx->ac.i32, array_size, false), "");
}
array_idx = LLVMBuildAdd(ctx->ac.builder, array_idx, offset, "");
deref_instr = nir_src_as_deref(deref_instr->parent);
} else {
unreachable("Unsupported deref type");
}
}
unsigned input_array_size = glsl_get_aoa_size(var->type);
if (!input_array_size)
input_array_size = 1;
for (chan = 0; chan < 4; chan++) {
LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->ac.f32, input_array_size));
LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
for (unsigned idx = 0; idx < input_array_size; ++idx) {
LLVMValueRef v, attr_number;
attr_number = LLVMConstInt(ctx->ac.i32, input_base + idx, false);
if (interp_param) {
interp_param = LLVMBuildBitCast(ctx->ac.builder,
interp_param, ctx->ac.v2f32, "");
......@@ -2889,15 +2924,19 @@ static LLVMValueRef visit_interp(struct ac_nir_context *ctx,
LLVMValueRef j = LLVMBuildExtractElement(
ctx->ac.builder, interp_param, ctx->ac.i32_1, "");
result[chan] = ac_build_fs_interp(&ctx->ac,
llvm_chan, attr_number,
v = ac_build_fs_interp(&ctx->ac, llvm_chan, attr_number,
ctx->abi->prim_mask, i, j);
} else {
result[chan] = ac_build_fs_interp_mov(&ctx->ac,
LLVMConstInt(ctx->ac.i32, 2, false),
llvm_chan, attr_number,
ctx->abi->prim_mask);
v = ac_build_fs_interp_mov(&ctx->ac, LLVMConstInt(ctx->ac.i32, 2, false),
llvm_chan, attr_number, ctx->abi->prim_mask);
}
gather = LLVMBuildInsertElement(ctx->ac.builder, gather, v,
LLVMConstInt(ctx->ac.i32, idx, false), "");
}
result[chan] = LLVMBuildExtractElement(ctx->ac.builder, gather, array_idx, "");
}
return ac_build_varying_gather_values(&ctx->ac, result, instr->num_components,
var->data.location_frac);
......@@ -3460,7 +3499,7 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr)
* It's unnecessary if the original texture format was
* Z32_FLOAT, but we don't know that here.
*/
if (args.compare && ctx->ac.chip_class == VI && ctx->abi->clamp_shadow_reference)
if (args.compare && ctx->ac.chip_class >= VI && ctx->abi->clamp_shadow_reference)
args.compare = ac_build_clamp(&ctx->ac, ac_to_float(&ctx->ac, args.compare));
/* pack derivatives */
......@@ -3851,7 +3890,7 @@ ac_handle_shader_output_decl(struct ac_llvm_context *ctx,
}
}
bool is_16bit = glsl_type_is_16bit(variable->type);
bool is_16bit = glsl_type_is_16bit(glsl_without_array(variable->type));
LLVMTypeRef type = is_16bit ? ctx->f16 : ctx->f32;
for (unsigned i = 0; i < attrib_count; ++i) {
for (unsigned chan = 0; chan < 4; chan++) {
......
src/amd/vulkan/radv_device.c
View file @ b1517248
......@@ -525,7 +525,7 @@ VkResult radv_CreateInstance(
pCreateInfo->pApplicationInfo->apiVersion != 0) {
client_version = pCreateInfo->pApplicationInfo->apiVersion;
} else {
radv_EnumerateInstanceVersion(&client_version);
client_version = VK_API_VERSION_1_0;
}
instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
......
src/amd/vulkan/radv_nir_to_llvm.c
View file @ b1517248
......@@ -256,7 +256,16 @@ get_tcs_num_patches(struct radv_shader_context *ctx)
/* Make sure that the data fits in LDS. This assumes the shaders only
* use LDS for the inputs and outputs.
*/
hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
hardware_lds_size = 32768;
/* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
* threadgroup, even though there is more than 32 KiB LDS.
*
* Test: dEQP-VK.tessellation.shader_input_output.barrier
*/
if (ctx->options->chip_class >= CIK && ctx->options->family != CHIP_STONEY)
hardware_lds_size = 65536;
num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
/* Make sure the output data fits in the offchip buffer */
num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
......@@ -2160,7 +2169,7 @@ handle_fs_input_decl(struct radv_shader_context *ctx,
interp = lookup_interp_param(&ctx->abi, variable->data.interpolation, interp_type);
}
bool is_16bit = glsl_type_is_16bit(variable->type);
bool is_16bit = glsl_type_is_16bit(glsl_without_array(variable->type));
LLVMTypeRef type = is_16bit ? ctx->ac.i16 : ctx->ac.i32;
if (interp == NULL)
interp = LLVMGetUndef(type);
......
src/amd/vulkan/radv_pipeline.c
View file @ b1517248
......@@ -3371,14 +3371,8 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
else
ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
ia_multi_vgt_param.partial_es_wave = false;
if (pipeline->device->has_distributed_tess) {
if (radv_pipeline_has_gs(pipeline)) {
if (device->physical_device->rad_info.chip_class <= VI)
ia_multi_vgt_param.partial_es_wave = true;
}
}
/* GS requirement. */
ia_multi_vgt_param.partial_es_wave = false;
if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= VI)
if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
ia_multi_vgt_param.partial_es_wave = true;
......@@ -3424,13 +3418,8 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
/* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
if (device->has_distributed_tess) {
if (radv_pipeline_has_gs(pipeline)) {
if (device->physical_device->rad_info.family == CHIP_TONGA ||
device->physical_device->rad_info.family == CHIP_FIJI ||
device->physical_device->rad_info.family == CHIP_POLARIS10 ||
device->physical_device->rad_info.family == CHIP_POLARIS11 ||
device->physical_device->rad_info.family == CHIP_POLARIS12 ||
device->physical_device->rad_info.family == CHIP_VEGAM)
ia_multi_vgt_param.partial_vs_wave = true;
if (device->physical_device->rad_info.chip_class <= VI)
ia_multi_vgt_param.partial_es_wave = true;
} else {
ia_multi_vgt_param.partial_vs_wave = true;
}
......@@ -3448,6 +3437,26 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
ia_multi_vgt_param.partial_vs_wave = true;
}
if (radv_pipeline_has_gs(pipeline)) {
/* On these chips there is the possibility of a hang if the
* pipeline uses a GS and partial_vs_wave is not set.
*
* This mostly does not hit 4-SE chips, as those typically set
* ia_switch_on_eoi and then partial_vs_wave is set for pipelines
* with GS due to another workaround.
*
* Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
*/
if (device->physical_device->rad_info.family == CHIP_TONGA ||
device->physical_device->rad_info.family == CHIP_FIJI ||
device->physical_device->rad_info.family == CHIP_POLARIS10 ||
device->physical_device->rad_info.family == CHIP_POLARIS11 ||
device->physical_device->rad_info.family == CHIP_POLARIS12 ||
device->physical_device->rad_info.family == CHIP_VEGAM) {
ia_multi_vgt_param.partial_vs_wave = true;
}
}
ia_multi_vgt_param.base =
S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
/* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
......
src/compiler/glsl/ast_function.cpp
View file @ b1517248
......@@ -363,13 +363,12 @@ copy_index_derefs_to_temps(ir_instruction *ir, void *data)
ir = a->array->as_dereference();
ir_rvalue *idx = a->array_index;
if (idx->as_dereference_variable()) {
ir_variable *var = idx->variable_referenced();
/* If the index is read only it cannot change so there is no need
* to copy it.
*/
if (var->data.read_only || var->data.memory_read_only)
if (!var || var->data.read_only || var->data.memory_read_only)
return;
ir_variable *tmp = new(d->mem_ctx) ir_variable(idx->type, "idx_tmp",
......@@ -389,7 +388,6 @@ copy_index_derefs_to_temps(ir_instruction *ir, void *data)
a->array_index = deref_tmp_2;
}
}
}
static void
fix_parameter(void *mem_ctx, ir_rvalue *actual, const glsl_type *formal_type,
......@@ -402,7 +400,8 @@ fix_parameter(void *mem_ctx, ir_rvalue *actual, const glsl_type *formal_type,
* nothing needs to be done to fix the parameter.
*/
if (formal_type == actual->type
&& (expr == NULL || expr->operation != ir_binop_vector_extract))
&& (expr == NULL || expr->operation != ir_binop_vector_extract)
&& actual->as_dereference_variable())
return;
/* An array index could also be an out variable so we need to make a copy
......@@ -456,7 +455,7 @@ fix_parameter(void *mem_ctx, ir_rvalue *actual, const glsl_type *formal_type,
ir_dereference_variable *const deref_tmp_1 =
new(mem_ctx) ir_dereference_variable(tmp);
ir_assignment *const assignment =
new(mem_ctx) ir_assignment(deref_tmp_1, actual);
new(mem_ctx) ir_assignment(deref_tmp_1, actual->clone(mem_ctx, NULL));
before_instructions->push_tail(assignment);
}
......
src/compiler/glsl/lower_output_reads.cpp
View file @ b1517248
......@@ -101,6 +101,10 @@ output_read_remover::visit(ir_dereference_variable *ir)
void *var_ctx = ralloc_parent(ir->var);
temp = new(var_ctx) ir_variable(ir->var->type, ir->var->name,
ir_var_temporary);
/* copy flags which affect arithematical precision */
temp->data.invariant = ir->var->data.invariant;
temp->data.precise = ir->var->data.precise;
temp->data.precision = ir->var->data.precision;
_mesa_hash_table_insert(replacements, ir->var, temp);
ir->var->insert_after(temp);
}
......
src/compiler/glsl/serialize.cpp
View file @ b1517248
......@@ -764,6 +764,12 @@ get_shader_var_and_pointer_sizes(size_t *s_var_size, size_t *s_var_ptrs,
sizeof(var->name);
}
enum uniform_type
{
uniform_remapped,
uniform_not_remapped
};
static void
write_program_resource_data(struct blob *metadata,
struct gl_shader_program *prog,
......@@ -816,6 +822,9 @@ write_program_resource_data(struct blob *metadata,
case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
case GL_UNIFORM:
if (((gl_uniform_storage *)res->Data)->builtin ||
res->Type != GL_UNIFORM) {
blob_write_uint32(metadata, uniform_not_remapped);
for (unsigned i = 0; i < prog->data->NumUniformStorage; i++) {
if (strcmp(((gl_uniform_storage *)res->Data)->name,
prog->data->UniformStorage[i].name) == 0) {
......@@ -823,6 +832,10 @@ write_program_resource_data(struct blob *metadata,
break;
}
}
} else {
blob_write_uint32(metadata, uniform_remapped);
blob_write_uint32(metadata, ((gl_uniform_storage *)res->Data)->remap_location);
}
break;
case GL_ATOMIC_COUNTER_BUFFER:
for (unsigned i = 0; i < prog->data->NumAtomicBuffers; i++) {
......@@ -906,9 +919,15 @@ read_program_resource_data(struct blob_reader *metadata,
case GL_COMPUTE_SUBROUTINE_UNIFORM:
case GL_TESS_CONTROL_SUBROUTINE_UNIFORM:
case GL_TESS_EVALUATION_SUBROUTINE_UNIFORM:
case GL_UNIFORM:
case GL_UNIFORM: {
enum uniform_type type = (enum uniform_type) blob_read_uint32(metadata);
if (type == uniform_not_remapped) {
res->Data = &prog->data->UniformStorage[blob_read_uint32(metadata)];
} else {
res->Data = prog->UniformRemapTable[blob_read_uint32(metadata)];
}
break;
}
case GL_ATOMIC_COUNTER_BUFFER:
res->Data = &prog->data->AtomicBuffers[blob_read_uint32(metadata)];
break;
......
src/compiler/nir/nir_gather_xfb_info.c
View file @ b1517248
......@@ -76,13 +76,13 @@ add_var_xfb_outputs(nir_xfb_info *xfb,
nir_xfb_output_info *output = &xfb->outputs[xfb->output_count++];
output->buffer = var->data.xfb_buffer;
output->offset = *offset;
output->offset = *offset + s * 16;
output->location = *location;
output->component_mask = (comp_mask >> (s * 4)) & 0xf;
(*location)++;
*offset += comp_slots * 4;
}
*offset += comp_slots * 4;
}
}
......
src/compiler/nir/nir_opt_copy_prop_vars.c
View file @ b1517248
......@@ -143,9 +143,19 @@ gather_vars_written(struct copy_prop_var_state *state,
written->modes = nir_var_shader_out;
break;
case nir_intrinsic_deref_atomic_add:
case nir_intrinsic_deref_atomic_imin:
case nir_intrinsic_deref_atomic_umin:
case nir_intrinsic_deref_atomic_imax:
case nir_intrinsic_deref_atomic_umax:
case nir_intrinsic_deref_atomic_and:
case nir_intrinsic_deref_atomic_or:
case nir_intrinsic_deref_atomic_xor:
case nir_intrinsic_deref_atomic_exchange:
case nir_intrinsic_deref_atomic_comp_swap:
case nir_intrinsic_store_deref:
case nir_intrinsic_copy_deref: {
/* Destination in _both_ store_deref and copy_deref is src[0]. */
/* Destination in all of store_deref, copy_deref and the atomics is src[0]. */
nir_deref_instr *dst = nir_src_as_deref(intrin->src[0]);
uintptr_t mask = intrin->intrinsic == nir_intrinsic_store_deref ?
......@@ -750,6 +760,19 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
break;
}
case nir_intrinsic_deref_atomic_add:
case nir_intrinsic_deref_atomic_imin:
case nir_intrinsic_deref_atomic_umin:
case nir_intrinsic_deref_atomic_imax:
case nir_intrinsic_deref_atomic_umax:
case nir_intrinsic_deref_atomic_and:
case nir_intrinsic_deref_atomic_or:
case nir_intrinsic_deref_atomic_xor:
case nir_intrinsic_deref_atomic_exchange:
case nir_intrinsic_deref_atomic_comp_swap:
kill_aliases(copies, nir_src_as_deref(intrin->src[0]), 0xf);
break;
default:
break;
}
......
src/gallium/drivers/etnaviv/etnaviv_context.c
View file @ b1517248
......@@ -60,6 +60,8 @@ etna_context_destroy(struct pipe_context *pctx)
{
struct etna_context *ctx = etna_context(pctx);
util_copy_framebuffer_state(&ctx->framebuffer_s, NULL);
if (ctx->primconvert)
util_primconvert_destroy(ctx->primconvert);
......@@ -296,10 +298,10 @@ etna_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
if (DBG_ENABLED(ETNA_DBG_FLUSH_ALL))
pctx->flush(pctx, NULL, 0);
if (ctx->framebuffer.cbuf)
etna_resource(ctx->framebuffer.cbuf->texture)->seqno++;
if (ctx->framebuffer.zsbuf)
etna_resource(ctx->framebuffer.zsbuf->texture)->seqno++;
if (ctx->framebuffer_s.cbufs[0])
etna_resource(ctx->framebuffer_s.cbufs[0]->texture)->seqno++;
if (ctx->framebuffer_s.zsbuf)
etna_resource(ctx->framebuffer_s.zsbuf->texture)->seqno++;
if (info->index_size && indexbuf != info->index.resource)
pipe_resource_reference(&indexbuf, NULL);
}
......
src/gallium/drivers/etnaviv/etnaviv_internal.h
View file @ b1517248
......@@ -182,7 +182,6 @@ struct compiled_viewport_state {
/* Compiled pipe_framebuffer_state */
struct compiled_framebuffer_state {
struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */
uint32_t GL_MULTI_SAMPLE_CONFIG;
uint32_t PE_COLOR_FORMAT;
uint32_t PE_DEPTH_CONFIG;
......