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bin/.cherry-ignore
View file @ 58e4d891
......@@ -3,3 +3,22 @@ ab0809e5529725bd0af6f7b6ce06415020b9d32e meson: fix strtof locale support check
# fixes: The commit addresses Meson which is explicitly disabled for 17.3
44fbbd6fd07e5784b05e08e762e54b6c71f95ab1 util: add mesa-sha1 test to meson
# stable: The commit is causing a regression
# (https://bugs.freedesktop.org/show_bug.cgi?id=103626)
18fde36ced4279f2577097a1a7d31b55f2f5f141 intel/fs: Use the original destination region for int MUL lowering
# stable: The commit addresses earlier commit 6132992cdb which did not land in
# branch
3d2b157e23c9d66df97d59be6efd1098878cc110 i965/fs: Use UW types when using V immediates
# extra: The commit just references a fix for an additional change in its v2.
c1ff99fd70cd2ceb2cac4723e4fd5efc93834746 main: Clear shader program data whenever ProgramBinary is called
# fixes: The commit addresses earlier commits 40a01c9a0ef and 8d745abc009 which
# did not land in branch
9b0223046668593deb9c0be0b557994bb5218788 egl: pass the dri2_dpy to the $plat_teardown functions
# fixes: The commit addresses earlier commit d50937f137 which did not land in
# branch
78a8b73e7d45f55ced98a148b26247d91f4e0171 vulkan/wsi: free cmd pools
debian/changelog
View file @ 58e4d891
mesa (17.3.1-0ubuntu1) UNRELEASED; urgency=medium
mesa (17.3.3-0ubuntu1) bionic; urgency=medium
* New upstream release.
* patches: Drop upstreamed patch, refresh egl-platform-mir.patch.
* rules: Fix disabling omx.
* libgbm1.symbols: Updated.
-- Timo Aaltonen <tjaalton@debian.org> Fri, 22 Dec 2017 17:29:54 +0200
-- Timo Aaltonen <tjaalton@debian.org> Fri, 26 Jan 2018 14:45:02 +0200
mesa (17.2.4-0ubuntu2) bionic; urgency=medium
......
docs/relnotes/17.3.1.html
View file @ 58e4d891
......@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
<h2>SHA256 checksums</h2>
<pre>
TBD
b0bb0419dbe3043ed4682a28eaf95721f427ca3f23a3c2a7dc77dbe8a3b6384d mesa-17.3.1.tar.gz
9ae607e0998a586fb2c866cfc8e45e6f52d1c56cb1b41288253ea83eada824c1 mesa-17.3.1.tar.xz
</pre>
......
docs/relnotes/17.3.2.html 0 → 100644
View file @ 58e4d891
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.3.2 Release Notes / January 8, 2018</h1>
<p>
Mesa 17.3.2 is a bug fix release which fixes bugs found since the 17.3.1 release.
</p>
<p>
Mesa 17.3.2 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
f997e80f14c385f9a2ba827c2b74aebf1b7426712ca4a81c631ef9f78e437bf4 mesa-17.3.2.tar.gz
e2844a13f2d6f8f24bee65804a51c42d8dc6ae9c36cff7ee61d0940e796d64c6 mesa-17.3.2.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=97852">Bug 97852</a> - Unreal Engine corrupted preview viewport</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=103801">Bug 103801</a> - [i965] &gt;Observer_ issue</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104288">Bug 104288</a> - Steamroll needs allow_glsl_cross_stage_interpolation_mismatch=true</li>
</ul>
<h2>Changes</h2>
<p>Bas Nieuwenhuizen (1):</p>
<ul>
<li>radv: Fix DCC compatible formats.</li>
</ul>
<p>Brendan King (1):</p>
<ul>
<li>egl: link libEGL against the dynamic version of libglapi</li>
</ul>
<p>Dave Airlie (6):</p>
<ul>
<li>radv/gfx9: add support for 3d images to blit 2d paths</li>
<li>radv: handle depth/stencil image copy with layouts better. (v3.1)</li>
<li>radv/meta: fix blit paths for depth/stencil (v2.1)</li>
<li>radv: fix issue with multisample positions and interp_var_at_sample.</li>
<li>radv/gfx9: add 3d sampler image-&gt;buffer copy shader. (v3)</li>
<li>radv: don't do format replacement on tc compat htile surfaces.</li>
</ul>
<p>Emil Velikov (2):</p>
<ul>
<li>docs: add sha256 checksums for 17.3.1</li>
<li>Update version to 17.3.2</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>egl: let each platform decided how to handle LIBGL_ALWAYS_SOFTWARE</li>
</ul>
<p>Rob Herring (1):</p>
<ul>
<li>egl/android: Fix build break with dri2_initialize_android _EGLDisplay parameter</li>
</ul>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv/gfx9: fix primitive topology when adjacency is used</li>
<li>radv: use a faster version for nir_op_pack_half_2x16</li>
</ul>
<p>Tapani Pälli (2):</p>
<ul>
<li>mesa: add AllowGLSLCrossStageInterpolationMismatch workaround</li>
<li>drirc: set allow_glsl_cross_stage_interpolation_mismatch for more games</li>
</ul>
</div>
</body>
</html>
docs/relnotes/17.3.3.html 0 → 100644
View file @ 58e4d891
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 17.3.3 Release Notes / January 18, 2018</h1>
<p>
Mesa 17.3.3 is a bug fix release which fixes bugs found since the 17.3.2 release.
</p>
<p>
Mesa 17.3.3 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation
because compatibility contexts are not supported.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104214">Bug 104214</a> - Dota crashes when switching from game to desktop</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104492">Bug 104492</a> - Compute Shader: Wrong alignment when assigning struct value to structured SSBO</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=104551">Bug 104551</a> - Check if Mako templates for Python are installed</li>
</ul>
<h2>Changes</h2>
<p>Alex Smith (3):</p>
<ul>
<li>anv: Add missing unlock in anv_scratch_pool_alloc</li>
<li>anv: Take write mask into account in has_color_buffer_write_enabled</li>
<li>anv: Make sure state on primary is correct after CmdExecuteCommands</li>
</ul>
<p>Andres Gomez (1):</p>
<ul>
<li>anv: Import mako templates only during execution of anv_extensions</li>
</ul>
<p>Bas Nieuwenhuizen (11):</p>
<ul>
<li>radv: Invert condition for all samples identical during resolve.</li>
<li>radv: Flush caches before subpass resolve.</li>
<li>radv: Fix fragment resolve destination offset.</li>
<li>radv: Use correct framebuffer size for partial FS resolves.</li>
<li>radv: Always use fragment resolve if dest uses DCC.</li>
<li>Revert "radv/gfx9: fix block compression texture views."</li>
<li>radv: Use correct HTILE expanded words.</li>
<li>radv: Allow writing 0 scissors.</li>
<li>ac/nir: Handle loading data from compact arrays.</li>
<li>radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT.</li>
<li>ac/nir: Sanitize location_frac for local variables.</li>
</ul>
<p>Dave Airlie (8):</p>
<ul>
<li>radv: fix events on compute queues.</li>
<li>radv: fix pipeline statistics end query on compute queue</li>
<li>radv/gfx9: fix 3d image to image transfers on compute queues.</li>
<li>radv/gfx9: fix 3d image clears on compute queues</li>
<li>radv/gfx9: fix buffer to image for 3d images on compute queues</li>
<li>radv/gfx9: fix block compression texture views.</li>
<li>radv/gfx9: use a bigger hammer to flush cb/db caches.</li>
<li>radv/gfx9: use correct swizzle parameter to work out border swizzle.</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>docs: add sha256 checksums for 17.3.2</li>
</ul>
<p>Florian Will (1):</p>
<ul>
<li>glsl: Respect std430 layout in lower_buffer_access</li>
</ul>
<p>Juan A. Suarez Romero (6):</p>
<ul>
<li>cherry-ignore: intel/fs: Use the original destination region for int MUL lowering</li>
<li>cherry-ignore: i965/fs: Use UW types when using V immediates</li>
<li>cherry-ignore: main: Clear shader program data whenever ProgramBinary is called</li>
<li>cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions</li>
<li>cherry-ignore: vulkan/wsi: free cmd pools</li>
<li>Update version to 17.3.3</li>
</ul>
<p>Józef Kucia (1):</p>
<ul>
<li>radeonsi: fix alpha-to-coverage if color writes are disabled</li>
</ul>
<p>Kenneth Graunke (2):</p>
<ul>
<li>i965: Require space for MI_BATCHBUFFER_END.</li>
<li>i965: Torch public intel_batchbuffer_emit_dword/float helpers.</li>
</ul>
<p>Lucas Stach (1):</p>
<ul>
<li>etnaviv: disable in-place resolve for non-supertiled surfaces</li>
</ul>
<p>Samuel Iglesias Gonsálvez (1):</p>
<ul>
<li>anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0</li>
</ul>
<p>Thomas Hellstrom (1):</p>
<ul>
<li>loader/dri3: Avoid freeing renderbuffers in use</li>
</ul>
<p>Tim Rowley (1):</p>
<ul>
<li>swr/rast: fix invalid sign masks in avx512 simdlib code</li>
</ul>
</div>
</body>
</html>
src/amd/common/ac_nir_to_llvm.c
View file @ 58e4d891
......@@ -1517,23 +1517,13 @@ static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
LLVMValueRef src0)
{
LLVMValueRef const16 = LLVMConstInt(ctx->i32, 16, false);
int i;
LLVMValueRef comp[2];
src0 = ac_to_float(ctx, src0);
comp[0] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_0, "");
comp[1] = LLVMBuildExtractElement(ctx->builder, src0, ctx->i32_1, "");
for (i = 0; i < 2; i++) {
comp[i] = LLVMBuildFPTrunc(ctx->builder, comp[i], ctx->f16, "");
comp[i] = LLVMBuildBitCast(ctx->builder, comp[i], ctx->i16, "");
comp[i] = LLVMBuildZExt(ctx->builder, comp[i], ctx->i32, "");
}
comp[1] = LLVMBuildShl(ctx->builder, comp[1], const16, "");
comp[0] = LLVMBuildOr(ctx->builder, comp[0], comp[1], "");
return comp[0];
return ac_build_cvt_pkrtz_f16(ctx, comp);
}
static LLVMValueRef emit_unpack_half_2x16(struct ac_llvm_context *ctx,
......@@ -3083,6 +3073,7 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
LLVMValueRef indir_index;
LLVMValueRef ret;
unsigned const_index;
unsigned stride = instr->variables[0]->var->data.compact ? 1 : 4;
bool vs_in = ctx->stage == MESA_SHADER_VERTEX &&
instr->variables[0]->var->data.mode == nir_var_shader_in;
get_deref_offset(ctx, instr->variables[0], vs_in, NULL, NULL,
......@@ -3108,13 +3099,13 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
count -= chan / 4;
LLVMValueRef tmp_vec = ac_build_gather_values_extended(
&ctx->ac, ctx->abi->inputs + idx + chan, count,
4, false, true);
stride, false, true);
values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
tmp_vec,
indir_index, "");
} else
values[chan] = ctx->abi->inputs[idx + chan + const_index * 4];
values[chan] = ctx->abi->inputs[idx + chan + const_index * stride];
}
break;
case nir_var_local:
......@@ -3125,13 +3116,13 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
count -= chan / 4;
LLVMValueRef tmp_vec = ac_build_gather_values_extended(
&ctx->ac, ctx->locals + idx + chan, count,
4, true, true);
stride, true, true);
values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
tmp_vec,
indir_index, "");
} else {
values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * 4], "");
values[chan] = LLVMBuildLoad(ctx->ac.builder, ctx->locals[idx + chan + const_index * stride], "");
}
}
break;
......@@ -3153,14 +3144,14 @@ static LLVMValueRef visit_load_var(struct ac_nir_context *ctx,
count -= chan / 4;
LLVMValueRef tmp_vec = ac_build_gather_values_extended(
&ctx->ac, ctx->outputs + idx + chan, count,
4, true, true);
stride, true, true);
values[chan] = LLVMBuildExtractElement(ctx->ac.builder,
tmp_vec,
indir_index, "");
} else {
values[chan] = LLVMBuildLoad(ctx->ac.builder,
ctx->outputs[idx + chan + const_index * 4],
ctx->outputs[idx + chan + const_index * stride],
"");
}
}
......@@ -5456,6 +5447,7 @@ setup_locals(struct ac_nir_context *ctx,
nir_foreach_variable(variable, &func->impl->locals) {
unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
variable->data.driver_location = ctx->num_locals * 4;
variable->data.location_frac = 0;
ctx->num_locals += attrib_count;
}
ctx->locals = malloc(4 * ctx->num_locals * sizeof(LLVMValueRef));
......
src/amd/vulkan/radv_cmd_buffer.c
View file @ 58e4d891
......@@ -541,7 +541,8 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
return;
radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
......@@ -1918,11 +1919,11 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
switch ((VkAccessFlagBits)(1 << b)) {
case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
case VK_ACCESS_INDEX_READ_BIT:
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
break;
case VK_ACCESS_UNIFORM_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
break;
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
case VK_ACCESS_SHADER_READ_BIT:
case VK_ACCESS_TRANSFER_READ_BIT:
case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
......@@ -3582,7 +3583,8 @@ void radv_CmdEndRenderPass(
/*
* For HTILE we have the following interesting clear words:
* 0x0000030f: Uncompressed.
* 0x0000030f: Uncompressed for depth+stencil HTILE.
* 0x0000000f: Uncompressed for depth only HTILE.
* 0xfffffff0: Clear depth to 1.0
* 0x00000000: Clear depth to 0.0
*/
......@@ -3631,7 +3633,8 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
radv_initialize_htile(cmd_buffer, image, range, 0);
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
radv_initialize_htile(cmd_buffer, image, range, 0xffffffff);
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
!radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
VkImageSubresourceRange local_range = *range;
......@@ -3833,7 +3836,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
si_cs_emit_write_event_eop(cs,
cmd_buffer->state.predicating,
cmd_buffer->device->physical_device->rad_info.chip_class,
false,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
1, va, 2, value);
......
src/amd/vulkan/radv_image.c
View file @ 58e4d891
......@@ -127,7 +127,7 @@ radv_init_surface(struct radv_device *device,
surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
bool dcc_compatible_formats = !radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
bool dcc_compatible_formats = radv_is_colorbuffer_format_supported(pCreateInfo->format, &blendable);
if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
const struct VkImageFormatListCreateInfoKHR *format_list =
(const struct VkImageFormatListCreateInfoKHR *)
......@@ -344,7 +344,7 @@ static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
}
}
static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
{
unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
......@@ -449,7 +449,7 @@ si_make_texture_descriptor(struct radv_device *device,
state[7] = 0;
if (device->physical_device->rad_info.chip_class >= GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
/* Depth is the the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
......
src/amd/vulkan/radv_meta.c
View file @ 58e4d891
......@@ -533,7 +533,7 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
nir_builder_instr_insert(b, &tex_all_same->instr);
nir_ssa_def *all_same = nir_ine(b, &tex_all_same->dest.ssa, nir_imm_int(b, 0));
nir_ssa_def *all_same = nir_ieq(b, &tex_all_same->dest.ssa, nir_imm_int(b, 0));
nir_if *if_stmt = nir_if_create(b->shader);
if_stmt->condition = nir_src_for_ssa(all_same);
nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
......
src/amd/vulkan/radv_meta.h
View file @ 58e4d891
......@@ -109,6 +109,7 @@ struct radv_meta_blit2d_surf {
unsigned level;
unsigned layer;
VkImageAspectFlags aspect_mask;
VkImageLayout current_layout;
};
struct radv_meta_blit2d_buffer {
......
src/amd/vulkan/radv_meta_blit.c
View file @ 58e4d891
......@@ -265,10 +265,12 @@ static void
meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image,
struct radv_image_view *src_iview,
VkImageLayout src_image_layout,
VkOffset3D src_offset_0,
VkOffset3D src_offset_1,
struct radv_image *dest_image,
struct radv_image_view *dest_iview,
VkImageLayout dest_image_layout,
VkOffset2D dest_offset_0,
VkOffset2D dest_offset_1,
VkRect2D dest_box,
......@@ -351,11 +353,12 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
}
break;
}
case VK_IMAGE_ASPECT_DEPTH_BIT:
case VK_IMAGE_ASPECT_DEPTH_BIT: {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
&(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit.depth_only_rp,
.renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
.framebuffer = fb,
.renderArea = {
.offset = { dest_box.offset.x, dest_box.offset.y },
......@@ -378,11 +381,13 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
unreachable(!"bad VkImageType");
}
break;
case VK_IMAGE_ASPECT_STENCIL_BIT:
}
case VK_IMAGE_ASPECT_STENCIL_BIT: {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
&(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit.stencil_only_rp,
.renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
.framebuffer = fb,
.renderArea = {
.offset = { dest_box.offset.x, dest_box.offset.y },
......@@ -405,6 +410,7 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
unreachable(!"bad VkImageType");
}
break;
}
default:
unreachable(!"bad VkImageType");
}
......@@ -620,9 +626,9 @@ void radv_CmdBlitImage(
},
});
meta_emit_blit(cmd_buffer,
src_image, &src_iview,
src_image, &src_iview, srcImageLayout,
src_offset_0, src_offset_1,
dest_image, &dest_iview,
dest_image, &dest_iview, destImageLayout,
dest_offset_0, dest_offset_1,
dest_box,
filter);
......@@ -652,8 +658,13 @@ radv_device_finish_meta_blit_state(struct radv_device *device)
&state->alloc);
}
for (enum radv_blit_ds_layout i = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; i < RADV_BLIT_DS_LAYOUT_COUNT; i++) {
radv_DestroyRenderPass(radv_device_to_handle(device),
state->blit.depth_only_rp[i], &state->alloc);
radv_DestroyRenderPass(radv_device_to_handle(device),
state->blit.depth_only_rp, &state->alloc);
state->blit.stencil_only_rp[i], &state->alloc);
}
radv_DestroyPipeline(radv_device_to_handle(device),
state->blit.depth_only_1d_pipeline, &state->alloc);
radv_DestroyPipeline(radv_device_to_handle(device),
......@@ -661,8 +672,6 @@ radv_device_finish_meta_blit_state(struct radv_device *device)
radv_DestroyPipeline(radv_device_to_handle(device),
state->blit.depth_only_3d_pipeline, &state->alloc);
radv_DestroyRenderPass(radv_device_to_handle(device),
state->blit.stencil_only_rp, &state->alloc);
radv_DestroyPipeline(radv_device_to_handle(device),
state->blit.stencil_only_1d_pipeline,
&state->alloc);
......@@ -673,6 +682,7 @@ radv_device_finish_meta_blit_state(struct radv_device *device)
state->blit.stencil_only_3d_pipeline,
&state->alloc);
radv_DestroyPipelineLayout(radv_device_to_handle(device),
state->blit.pipeline_layout, &state->alloc);
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
......@@ -866,6 +876,8 @@ radv_device_init_meta_blit_depth(struct radv_device *device,
fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
result = radv_CreateRenderPass(radv_device_to_handle(device),
&(VkRenderPassCreateInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
......@@ -874,8 +886,8 @@ radv_device_init_meta_blit_depth(struct radv_device *device,
.format = VK_FORMAT_D32_SFLOAT,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
.initialLayout = layout,
.finalLayout = layout,
},
.subpassCount = 1,
.pSubpasses = &(VkSubpassDescription) {
......@@ -886,15 +898,16 @@ radv_device_init_meta_blit_depth(struct radv_device *device,
.pResolveAttachments = NULL,
.pDepthStencilAttachment = &(VkAttachmentReference) {
.attachment = 0,
.layout = VK_IMAGE_LAYOUT_GENERAL,
.layout = layout,
},
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
.dependencyCount = 0,
}, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
}, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
if (result != VK_SUCCESS)
goto fail;
}
VkPipelineVertexInputStateCreateInfo vi_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
......@@ -974,7 +987,7 @@ radv_device_init_meta_blit_depth(struct radv_device *device,
},
.flags = 0,
.layout = device->meta_state.blit.pipeline_layout,
.renderPass = device->meta_state.blit.depth_only_rp,
.renderPass = device->meta_state.blit.depth_only_rp[0],
.subpass = 0,
};
......@@ -1024,6 +1037,8 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
result = radv_CreateRenderPass(radv_device_to_handle(device),
&(VkRenderPassCreateInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
......@@ -1032,8 +1047,8 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
.format = VK_FORMAT_S8_UINT,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
.initialLayout = VK_IMAGE_LAYOUT_GENERAL,
.finalLayout = VK_IMAGE_LAYOUT_GENERAL,
.initialLayout = layout,
.finalLayout = layout,
},
.subpassCount = 1,
.pSubpasses = &(VkSubpassDescription) {
......@@ -1044,13 +1059,14 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
.pResolveAttachments = NULL,
.pDepthStencilAttachment = &(VkAttachmentReference) {
.attachment = 0,
.layout = VK_IMAGE_LAYOUT_GENERAL,
.layout = layout,
},
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
.dependencyCount = 0,
}, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
}, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
}
if (result != VK_SUCCESS)
goto fail;
......@@ -1134,7 +1150,6 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
},
.depthCompareOp = VK_COMPARE_OP_ALWAYS,
},
.pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
.sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
.dynamicStateCount = 6,
......@@ -1149,7 +1164,7 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
},
.flags = 0,
.layout = device->meta_state.blit.pipeline_layout,
.renderPass = device->meta_state.blit.stencil_only_rp,
.renderPass = device->meta_state.blit.stencil_only_rp[0],
.subpass = 0,
};
......@@ -1181,6 +1196,7 @@ radv_device_init_meta_blit_stencil(struct radv_device *device,
if (result != VK_SUCCESS)
goto fail;
fail:
ralloc_free(fs_1d.nir);
ralloc_free(fs_2d.nir);
......
src/amd/vulkan/radv_meta_blit2d.c
View file @ 58e4d891
......@@ -30,6 +30,7 @@
enum blit2d_src_type {
BLIT2D_SRC_TYPE_IMAGE,
BLIT2D_SRC_TYPE_IMAGE_3D,
BLIT2D_SRC_TYPE_BUFFER,
BLIT2D_NUM_SRC_TYPES,
};
......@@ -41,6 +42,8 @@ create_iview(struct radv_cmd_buffer *cmd_buffer,
VkImageAspectFlagBits aspects)
{
VkFormat format;
VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_IMAGE_VIEW_TYPE_2D :
radv_meta_get_view_type(surf->image);
if (depth_format)
format = depth_format;
......@@ -51,7 +54,7 @@ create_iview(struct radv_cmd_buffer *cmd_buffer,
&(VkImageViewCreateInfo) {
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
.image = radv_image_to_handle(surf->image),
.viewType = VK_IMAGE_VIEW_TYPE_2D,
.viewType = view_type,
.format = format,
.subresourceRange = {
.aspectMask = aspects,
......@@ -126,6 +129,12 @@ blit2d_bind_src(struct radv_cmd_buffer *cmd_buffer,
} else {
create_iview(cmd_buffer, src_img, &tmp->iview, depth_format, aspects);
if (src_type == BLIT2D_SRC_TYPE_IMAGE_3D)
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
device->meta_state.blit2d.p_layouts[src_type],
VK_SHADER_STAGE_FRAGMENT_BIT, 16, 4,
&src_img->layer);
radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
device->meta_state.blit2d.p_layouts[src_type],
0, /* set */
......@@ -269,10 +278,11 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
bind_pipeline(cmd_buffer, src_type, fs_key);
} else if (aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
&(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit2d.depth_only_rp,
.renderPass = device->meta_state.blit2d.depth_only_rp[ds_layout],
.framebuffer = dst_temps.fb,
.renderArea = {
.offset = { rects[r].dst_x, rects[r].dst_y, },
......@@ -286,10 +296,11 @@ radv_meta_blit2d_normal_dst(struct radv_cmd_buffer *cmd_buffer,
bind_depth_pipeline(cmd_buffer, src_type);
} else if (aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dst->current_layout);
radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
&(VkRenderPassBeginInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
.renderPass = device->meta_state.blit2d.stencil_only_rp,
.renderPass = device->meta_state.blit2d.stencil_only_rp[ds_layout],
.framebuffer = dst_temps.fb,
.renderArea = {
.offset = { rects[r].dst_x, rects[r].dst_y, },
......@@ -341,8 +352,10 @@ radv_meta_blit2d(struct radv_cmd_buffer *cmd_buffer,
unsigned num_rects,
struct radv_meta_blit2d_rect *rects)
{
bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
(src_img && src_img->image->type == VK_IMAGE_TYPE_3D);
enum blit2d_src_type src_type = src_buf ? BLIT2D_SRC_TYPE_BUFFER :
BLIT2D_SRC_TYPE_IMAGE;
use_3d ? BLIT2D_SRC_TYPE_IMAGE_3D : BLIT2D_SRC_TYPE_IMAGE;
radv_meta_blit2d_normal_dst(cmd_buffer, src_img, src_buf, dst,
num_rects, rects, src_type);
}
......@@ -407,29 +420,46 @@ build_nir_vertex_shader(void)
typedef nir_ssa_def* (*texel_fetch_build_func)(struct nir_builder *,
struct radv_device *,
nir_ssa_def *);
nir_ssa_def *, bool);
static nir_ssa_def *
build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
nir_ssa_def *tex_pos)
nir_ssa_def *tex_pos, bool is_3d)
{
enum glsl_sampler_dim dim = is_3d ? GLSL_SAMPLER_DIM_3D : GLSL_SAMPLER_DIM_2D;
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_2D, false, false, GLSL_TYPE_UINT);
glsl_sampler_type(dim, false, false, GLSL_TYPE_UINT);
nir_variable *sampler = nir_variable_create(b->shader, nir_var_uniform,
sampler_type, "s_tex");
sampler->data.descriptor_set = 0;
sampler->data.binding = 0;
nir_ssa_def *tex_pos_3d = NULL;
if (is_3d) {
nir_intrinsic_instr *layer = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_push_constant);
nir_intrinsic_set_base(layer, 16);
nir_intrinsic_set_range(layer, 4);
layer->src[0] = nir_src_for_ssa(nir_imm_int(b, 0));
layer->num_components = 1;
nir_ssa_dest_init(&layer->instr, &layer->dest, 1, 32, "layer");
nir_builder_instr_insert(b, &layer->instr);
nir_ssa_def *chans[3];
chans[0] = nir_channel(b, tex_pos, 0);
chans[1] = nir_channel(b, tex_pos, 1);
chans[2] = &layer->dest.ssa;
tex_pos_3d = nir_vec(b, chans, 3);
}
nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
tex->sampler_dim = GLSL_SAMPLER_DIM_2D;
tex->sampler_dim = dim;
tex->op = nir_texop_txf;
tex->src[0].src_type = nir_tex_src_coord;
tex->src[0].src = nir_src_for_ssa(tex_pos);
tex->src[0].src = nir_src_for_ssa(is_3d ? tex_pos_3d : tex_pos);
tex->src[1].src_type = nir_tex_src_lod;
tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
tex->dest_type = nir_type_uint;
tex->is_array = false;
tex->coord_components = 2;
tex->coord_components = is_3d ? 3 : 2;
tex->texture = nir_deref_var_create(tex, sampler);
tex->sampler = NULL;
......@@ -442,7 +472,7 @@ build_nir_texel_fetch(struct nir_builder *b, struct radv_device *device,
static nir_ssa_def *
build_nir_buffer_fetch(struct nir_builder *b, struct radv_device *device,
nir_ssa_def *tex_pos)
nir_ssa_def *tex_pos, bool is_3d)
{
const struct glsl_type *sampler_type =
glsl_sampler_type(GLSL_SAMPLER_DIM_BUF, false, false, GLSL_TYPE_UINT);
......@@ -490,7 +520,7 @@ static const VkPipelineVertexInputStateCreateInfo normal_vi_create_info = {
static nir_shader *
build_nir_copy_fragment_shader(struct radv_device *device,
texel_fetch_build_func txf_func, const char* name)
texel_fetch_build_func txf_func, const char* name, bool is_3d)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
......@@ -511,7 +541,7 @@ build_nir_copy_fragment_shader(struct radv_device *device,
unsigned swiz[4] = { 0, 1 };
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
nir_ssa_def *color = txf_func(&b, device, tex_pos);
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
nir_store_var(&b, color_out, color, 0xf);
return b.shader;
......@@ -519,7 +549,7 @@ build_nir_copy_fragment_shader(struct radv_device *device,
static nir_shader *
build_nir_copy_fragment_shader_depth(struct radv_device *device,
texel_fetch_build_func txf_func, const char* name)
texel_fetch_build_func txf_func, const char* name, bool is_3d)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
......@@ -540,7 +570,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,
unsigned swiz[4] = { 0, 1 };
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
nir_ssa_def *color = txf_func(&b, device, tex_pos);
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
nir_store_var(&b, color_out, color, 0x1);
return b.shader;
......@@ -548,7 +578,7 @@ build_nir_copy_fragment_shader_depth(struct radv_device *device,
static nir_shader *
build_nir_copy_fragment_shader_stencil(struct radv_device *device,
texel_fetch_build_func txf_func, const char* name)
texel_fetch_build_func txf_func, const char* name, bool is_3d)
{
const struct glsl_type *vec4 = glsl_vec4_type();
const struct glsl_type *vec2 = glsl_vector_type(GLSL_TYPE_FLOAT, 2);
......@@ -569,7 +599,7 @@ build_nir_copy_fragment_shader_stencil(struct radv_device *device,
unsigned swiz[4] = { 0, 1 };
nir_ssa_def *tex_pos = nir_swizzle(&b, pos_int, swiz, 2, false);
nir_ssa_def *color = txf_func(&b, device, tex_pos);
nir_ssa_def *color = txf_func(&b, device, tex_pos, is_3d);
nir_store_var(&b, color_out, color, 0x1);
return b.shader;
......@@ -586,10 +616,12 @@ radv_device_finish_meta_blit2d_state(struct radv_device *device)
&state->alloc);
}
for (enum radv_blit_ds_layout j = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; j < RADV_BLIT_DS_LAYOUT_COUNT; j++) {
radv_DestroyRenderPass(radv_device_to_handle(device),
state->blit2d.depth_only_rp, &state->alloc);
state->blit2d.depth_only_rp[j], &state->alloc);
radv_DestroyRenderPass(radv_device_to_handle(device),
state->blit2d.stencil_only_rp, &state->alloc);
state->blit2d.stencil_only_rp[j], &state->alloc);
}
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
radv_DestroyPipelineLayout(radv_device_to_handle(device),
......@@ -629,6 +661,10 @@ blit2d_init_color_pipeline(struct radv_device *device,
src_func = build_nir_texel_fetch;
name = "meta_blit2d_image_fs";
break;
case BLIT2D_SRC_TYPE_IMAGE_3D:
src_func = build_nir_texel_fetch;
name = "meta_blit3d_image_fs";
break;
case BLIT2D_SRC_TYPE_BUFFER:
src_func = build_nir_buffer_fetch;
name = "meta_blit2d_buffer_fs";
......@@ -642,7 +678,7 @@ blit2d_init_color_pipeline(struct radv_device *device,
struct radv_shader_module fs = { .nir = NULL };
fs.nir = build_nir_copy_fragment_shader(device, src_func, name);
fs.nir = build_nir_copy_fragment_shader(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
vi_create_info = &normal_vi_create_info;
struct radv_shader_module vs = {
......@@ -788,6 +824,10 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
src_func = build_nir_texel_fetch;
name = "meta_blit2d_depth_image_fs";
break;
case BLIT2D_SRC_TYPE_IMAGE_3D:
src_func = build_nir_texel_fetch;
name = "meta_blit3d_depth_image_fs";
break;
case BLIT2D_SRC_TYPE_BUFFER:
src_func = build_nir_buffer_fetch;
name = "meta_blit2d_depth_buffer_fs";
......@@ -800,7 +840,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
struct radv_shader_module fs = { .nir = NULL };
fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name);
fs.nir = build_nir_copy_fragment_shader_depth(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
vi_create_info = &normal_vi_create_info;
struct radv_shader_module vs = {
......@@ -823,7 +863,9 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
},
};
if (!device->meta_state.blit2d.depth_only_rp) {
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
if (!device->meta_state.blit2d.depth_only_rp[ds_layout]) {
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
result = radv_CreateRenderPass(radv_device_to_handle(device),
&(VkRenderPassCreateInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
......@@ -832,8 +874,8 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
.format = VK_FORMAT_D32_SFLOAT,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
.initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.initialLayout = layout,
.finalLayout = layout,
},
.subpassCount = 1,
.pSubpasses = &(VkSubpassDescription) {
......@@ -844,13 +886,14 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
.pResolveAttachments = NULL,
.pDepthStencilAttachment = &(VkAttachmentReference) {
.attachment = 0,
.layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.layout = layout,
},
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
.dependencyCount = 0,
}, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp);
}, &device->meta_state.alloc, &device->meta_state.blit2d.depth_only_rp[ds_layout]);
}
}
const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
......@@ -909,7 +952,7 @@ blit2d_init_depth_only_pipeline(struct radv_device *device,
},
.flags = 0,
.layout = device->meta_state.blit2d.p_layouts[src_type],
.renderPass = device->meta_state.blit2d.depth_only_rp,
.renderPass = device->meta_state.blit2d.depth_only_rp[0],
.subpass = 0,
};
......@@ -943,6 +986,10 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
src_func = build_nir_texel_fetch;
name = "meta_blit2d_stencil_image_fs";
break;
case BLIT2D_SRC_TYPE_IMAGE_3D:
src_func = build_nir_texel_fetch;
name = "meta_blit3d_stencil_image_fs";
break;
case BLIT2D_SRC_TYPE_BUFFER:
src_func = build_nir_buffer_fetch;
name = "meta_blit2d_stencil_buffer_fs";
......@@ -955,7 +1002,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
const VkPipelineVertexInputStateCreateInfo *vi_create_info;
struct radv_shader_module fs = { .nir = NULL };
fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name);
fs.nir = build_nir_copy_fragment_shader_stencil(device, src_func, name, src_type == BLIT2D_SRC_TYPE_IMAGE_3D);
vi_create_info = &normal_vi_create_info;
struct radv_shader_module vs = {
......@@ -978,7 +1025,9 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
},
};
if (!device->meta_state.blit2d.stencil_only_rp) {
for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
if (!device->meta_state.blit2d.stencil_only_rp[ds_layout]) {
VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
result = radv_CreateRenderPass(radv_device_to_handle(device),
&(VkRenderPassCreateInfo) {
.sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
......@@ -987,8 +1036,8 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
.format = VK_FORMAT_S8_UINT,
.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
.storeOp = VK_ATTACHMENT_STORE_OP_STORE,
.initialLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.finalLayout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.initialLayout = layout,
.finalLayout = layout,
},
.subpassCount = 1,
.pSubpasses = &(VkSubpassDescription) {
......@@ -999,13 +1048,14 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
.pResolveAttachments = NULL,
.pDepthStencilAttachment = &(VkAttachmentReference) {
.attachment = 0,
.layout = VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL,
.layout = layout,
},
.preserveAttachmentCount = 1,
.pPreserveAttachments = (uint32_t[]) { 0 },
},
.dependencyCount = 0,
}, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp);
}, &device->meta_state.alloc, &device->meta_state.blit2d.stencil_only_rp[ds_layout]);
}
}
const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
......@@ -1080,7 +1130,7 @@ blit2d_init_stencil_only_pipeline(struct radv_device *device,
},
.flags = 0,
.layout = device->meta_state.blit2d.p_layouts[src_type],
.renderPass = device->meta_state.blit2d.stencil_only_rp,
.renderPass = device->meta_state.blit2d.stencil_only_rp[0],
.subpass = 0,
};
......@@ -1120,6 +1170,7 @@ VkResult
radv_device_init_meta_blit2d_state(struct radv_device *device)
{
VkResult result;
bool create_3d = device->physical_device->rad_info.chip_class >= GFX9;
const VkPushConstantRange push_constant_ranges[] = {
{VK_SHADER_STAGE_VERTEX_BIT, 0, 16},
......@@ -1155,6 +1206,37 @@ radv_device_init_meta_blit2d_state(struct radv_device *device)
if (result != VK_SUCCESS)
goto fail;
if (create_3d) {
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
&(VkDescriptorSetLayoutCreateInfo) {
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
.bindingCount = 1,
.pBindings = (VkDescriptorSetLayoutBinding[]) {
{
.binding = 0,
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
.descriptorCount = 1,
.stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
.pImmutableSamplers = NULL
},
}
}, &device->meta_state.alloc, &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE_3D]);
if (result != VK_SUCCESS)
goto fail;
result = radv_CreatePipelineLayout(radv_device_to_handle(device),
&(VkPipelineLayoutCreateInfo) {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
.setLayoutCount = 1,
.pSetLayouts = &device->meta_state.blit2d.ds_layouts[BLIT2D_SRC_TYPE_IMAGE_3D],
.pushConstantRangeCount = 2,
.pPushConstantRanges = push_constant_ranges,
},
&device->meta_state.alloc, &device->meta_state.blit2d.p_layouts[BLIT2D_SRC_TYPE_IMAGE_3D]);
if (result != VK_SUCCESS)
goto fail;
}
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
&(VkDescriptorSetLayoutCreateInfo) {
.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
......@@ -1187,6 +1269,8 @@ radv_device_init_meta_blit2d_state(struct radv_device *device)
goto fail;
for (unsigned src = 0; src < BLIT2D_NUM_SRC_TYPES; src++) {
if (src == BLIT2D_SRC_TYPE_IMAGE_3D && !create_3d)
continue;
for (unsigned j = 0; j < ARRAY_SIZE(pipeline_formats); ++j) {
result = blit2d_init_color_pipeline(device, src, pipeline_formats[j]);
if (result != VK_SUCCESS)
......
src/amd/vulkan/radv_meta_bufimage.c
View file @ 58e4d891
This diff is collapsed.
src/amd/vulkan/radv_meta_copy.c
View file @ 58e4d891
......@@ -79,6 +79,7 @@ vk_format_for_size(int bs)
static struct radv_meta_blit2d_surf
blit_surf_for_image_level_layer(struct radv_image *image,
VkImageLayout layout,
const VkImageSubresourceLayers *subres)
{
VkFormat format = image->vk_format;
......@@ -87,7 +88,8 @@ blit_surf_for_image_level_layer(struct radv_image *image,
else if (subres->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT)
format = vk_format_stencil_only(format);
if (!image->surface.dcc_size)
if (!image->surface.dcc_size &&
!(image->surface.htile_size && image->tc_compatible_htile))
format = vk_format_for_size(vk_format_get_blocksize(format));
return (struct radv_meta_blit2d_surf) {
......@@ -97,6 +99,7 @@ blit_surf_for_image_level_layer(struct radv_image *image,
.layer = subres->baseArrayLayer,
.image = image,
.aspect_mask = subres->aspectMask,
.current_layout = layout,
};
}
......@@ -104,6 +107,7 @@ static void
meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
struct radv_buffer* buffer,
struct radv_image* image,
VkImageLayout layout,
uint32_t regionCount,
const VkBufferImageCopy* pRegions)
{
......@@ -155,6 +159,7 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer,
/* Create blit surfaces */
struct radv_meta_blit2d_surf img_bsurf =
blit_surf_for_image_level_layer(image,
layout,
&pRegions[r].imageSubresource);
struct radv_meta_blit2d_buffer buf_bsurf = {
......@@ -214,7 +219,7 @@ void radv_CmdCopyBufferToImage(
RADV_FROM_HANDLE(radv_image, dest_image, destImage);
RADV_FROM_HANDLE(radv_buffer, src_buffer, srcBuffer);
meta_copy_buffer_to_image(cmd_buffer, src_buffer, dest_image,
meta_copy_buffer_to_image(cmd_buffer, src_buffer, dest_image, destImageLayout,
regionCount, pRegions);
}
......@@ -222,6 +227,7 @@ static void
meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
struct radv_buffer* buffer,
struct radv_image* image,
VkImageLayout layout,
uint32_t regionCount,
const VkBufferImageCopy* pRegions)
{
......@@ -266,6 +272,7 @@ meta_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer,
/* Create blit surfaces */
struct radv_meta_blit2d_surf img_info =
blit_surf_for_image_level_layer(image,
layout,
&pRegions[r].imageSubresource);
struct radv_meta_blit2d_buffer buf_info = {
......@@ -318,13 +325,16 @@ void radv_CmdCopyImageToBuffer(
RADV_FROM_HANDLE(radv_buffer, dst_buffer, destBuffer);
meta_copy_image_to_buffer(cmd_buffer, dst_buffer, src_image,
srcImageLayout,
regionCount, pRegions);
}
static void
meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image,
VkImageLayout src_image_layout,
struct radv_image *dest_image,
VkImageLayout dest_image_layout,
uint32_t regionCount,
const VkImageCopy *pRegions)
{
......@@ -351,10 +361,12 @@ meta_copy_image(struct radv_cmd_buffer *cmd_buffer,
/* Create blit surfaces */
struct radv_meta_blit2d_surf b_src =
blit_surf_for_image_level_layer(src_image,
src_image_layout,
&pRegions[r].srcSubresource);
struct radv_meta_blit2d_surf b_dst =
blit_surf_for_image_level_layer(dest_image,
dest_image_layout,
&pRegions[r].dstSubresource);
/* for DCC */
......@@ -429,7 +441,9 @@ void radv_CmdCopyImage(
RADV_FROM_HANDLE(radv_image, src_image, srcImage);
RADV_FROM_HANDLE(radv_image, dest_image, destImage);
meta_copy_image(cmd_buffer, src_image, dest_image,
meta_copy_image(cmd_buffer,
src_image, srcImageLayout,
dest_image, destImageLayout,
regionCount, pRegions);
}
......@@ -449,6 +463,7 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer *cmd_buffer,
image_copy.extent.height = image->info.height;
image_copy.extent.depth = 1;
meta_copy_image(cmd_buffer, image, linear_image,
meta_copy_image(cmd_buffer, image, VK_IMAGE_LAYOUT_GENERAL, linear_image,
VK_IMAGE_LAYOUT_GENERAL,
1, &image_copy);
}
src/amd/vulkan/radv_meta_resolve.c
View file @ 58e4d891
......@@ -300,10 +300,9 @@ static void radv_pick_resolve_method_images(struct radv_image *src_image,
enum radv_resolve_method *method)
{
if (dest_image->surface.micro_tile_mode != src_image->surface.micro_tile_mode) {
if (dest_image->surface.num_dcc_levels > 0)
if (dest_image->surface.num_dcc_levels > 0) {
*method = RESOLVE_FRAGMENT;
else
} else if (dest_image->surface.micro_tile_mode != src_image->surface.micro_tile_mode) {
*method = RESOLVE_COMPUTE;
}
}
......
src/amd/vulkan/radv_meta_resolve_cs.c
View file @ 58e4d891
......@@ -487,6 +487,14 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
if (!subpass->has_resolve)
return;
/* Resolves happen before the end-of-subpass barriers get executed,
* so we have to make the attachment shader-readable */
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
RADV_CMD_FLAG_INV_VMEM_L1;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
VkAttachmentReference src_att = subpass->color_attachments[i];
VkAttachmentReference dest_att = subpass->resolve_attachments[i];
......
src/amd/vulkan/radv_meta_resolve_fs.c
View file @ 58e4d891
......@@ -407,8 +407,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
unsigned push_constants[2] = {
src_offset->x,
src_offset->y,
src_offset->x - dest_offset->x,
src_offset->y - dest_offset->y,
};
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
device->meta_state.resolve_fragment.p_layout,
......@@ -540,8 +540,8 @@ void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
.pAttachments = (VkImageView[]) {
radv_image_view_to_handle(&dest_iview),
},
.width = extent.width,
.height = extent.height,
.width = extent.width + dstOffset.x,
.height = extent.height + dstOffset.y,
.layers = 1
}, &cmd_buffer->pool->alloc, &fb);
......@@ -604,6 +604,16 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
RADV_META_SAVE_CONSTANTS |
RADV_META_SAVE_DESCRIPTORS);
/* Resolves happen before the end-of-subpass barriers get executed,
* so we have to make the attachment shader-readable */
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
RADV_CMD_FLAG_FLUSH_AND_INV_DB |
RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
RADV_CMD_FLAG_INV_GLOBAL_L2 |
RADV_CMD_FLAG_INV_VMEM_L1;
for (uint32_t i = 0; i < subpass->color_count; ++i) {
VkAttachmentReference src_att = subpass->color_attachments[i];
VkAttachmentReference dest_att = subpass->resolve_attachments[i];
......
src/amd/vulkan/radv_pipeline.c
View file @ 58e4d891
......@@ -1175,7 +1175,7 @@ static void calculate_gfx9_gs_info(const VkGraphicsPipelineCreateInfo *pCreateIn
case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
uses_adjacency = false;
uses_adjacency = true;
break;
default:
uses_adjacency = false;
......
src/amd/vulkan/radv_private.h
View file @ 58e4d891
......@@ -348,6 +348,22 @@ radv_pipeline_cache_insert_shaders(struct radv_device *device,
const void *const *codes,
const unsigned *code_sizes);
enum radv_blit_ds_layout {
RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
RADV_BLIT_DS_LAYOUT_COUNT,
};
static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
{
return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
}
static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
{
return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
}
struct radv_meta_state {
VkAllocationCallbacks alloc;
......@@ -380,12 +396,12 @@ struct radv_meta_state {
/** Pipeline that blits from a 3D image. */
VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
VkRenderPass depth_only_rp;
VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline depth_only_1d_pipeline;
VkPipeline depth_only_2d_pipeline;
VkPipeline depth_only_3d_pipeline;
VkRenderPass stencil_only_rp;
VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline stencil_only_1d_pipeline;
VkPipeline stencil_only_2d_pipeline;
VkPipeline stencil_only_3d_pipeline;
......@@ -396,36 +412,40 @@ struct radv_meta_state {
struct {
VkRenderPass render_passes[NUM_META_FS_KEYS];
VkPipelineLayout p_layouts[2];
VkDescriptorSetLayout ds_layouts[2];
VkPipeline pipelines[2][NUM_META_FS_KEYS];
VkPipelineLayout p_layouts[3];
VkDescriptorSetLayout ds_layouts[3];
VkPipeline pipelines[3][NUM_META_FS_KEYS];
VkRenderPass depth_only_rp;
VkPipeline depth_only_pipeline[2];
VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline depth_only_pipeline[3];
VkRenderPass stencil_only_rp;
VkPipeline stencil_only_pipeline[2];
VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
VkPipeline stencil_only_pipeline[3];
} blit2d;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} itob;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} btoi;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} itoi;
struct {
VkPipelineLayout img_p_layout;
VkDescriptorSetLayout img_ds_layout;
VkPipeline pipeline;
VkPipeline pipeline_3d;
} cleari;
struct {
......