...
 
Commits (20)
......@@ -49,7 +49,6 @@ def main():
if os.path.lexists(to):
os.unlink(to)
os.makedirs(to)
shutil.copy(args.megadriver, master)
for driver in args.drivers:
abs_driver = os.path.join(to, driver)
......
mesa (19.0.1-2) UNRELEASED; urgency=medium
mesa (19.0.2-1) experimental; urgency=medium
* New upstream release.
* control: Bump libdrm-dev build-dep, amdgpu needs 2.4.97.
-- Timo Aaltonen <tjaalton@debian.org> Wed, 10 Apr 2019 12:58:36 +0300
-- Timo Aaltonen <tjaalton@debian.org> Thu, 11 Apr 2019 11:50:26 +0300
mesa (19.0.1-1) experimental; urgency=medium
......
......@@ -31,7 +31,8 @@ Compatibility contexts may report a lower version depending on each driver.
<h2>SHA256 checksums</h2>
<pre>
TBD
f1dd1980ed628edea3935eed7974fbc5d8353e9578c562728b880d63ac613dbd mesa-19.0.1.tar.gz
6884163c0ea9e4c98378ab8fecd72fe7b5f437713a14471beda378df247999d4 mesa-19.0.1.tar.xz
</pre>
......
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.0.2 Release Notes / April 10, 2019</h1>
<p>
Mesa 19.0.2 is a bug fix release which fixes bugs found since the 19.0.1 release.
</p>
<p>
Mesa 19.0.2 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
TBD
</pre>
<h2>New features</h2>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=108766">Bug 108766</a> - Mesa built with meson has RPATH entries</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=109648">Bug 109648</a> - AMD Raven hang during va-api decoding</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110257">Bug 110257</a> - Major artifacts in mpeg2 vaapi hw decoding</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110259">Bug 110259</a> - radv: Sampling depth-stencil image in GENERAL layout returns nothing but zero (regression, bisected)</li>
</ul>
<h2>Changes</h2>
<p>Boyuan Zhang (1):</p>
<ul>
<li>st/va: reverse qt matrix back to its original order</li>
</ul>
<p>Caio Marcelo de Oliveira Filho (1):</p>
<ul>
<li>nir: Take if_uses into account when repairing SSA</li>
</ul>
<p>Dylan Baker (2):</p>
<ul>
<li>docs: Add SHA256 sums for mesa 19.0.1</li>
<li>VERSION: bump version for 19.0.2</li>
</ul>
<p>Eric Anholt (3):</p>
<ul>
<li>dri3: Return the current swap interval from glXGetSwapIntervalMESA().</li>
<li>v3d: Bump the maximum texture size to 4k for V3D 4.x.</li>
<li>v3d: Don't try to use the TFU blit path if a scissor is enabled.</li>
</ul>
<p>Eric Engestrom (1):</p>
<ul>
<li>meson: strip rpath from megadrivers</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"</li>
</ul>
<p>Karol Herbst (1):</p>
<ul>
<li>nir/print: fix printing the image_array intrinsic index</li>
</ul>
<p>Leo Liu (2):</p>
<ul>
<li>radeon/vcn: add H.264 constrained baseline support</li>
<li>radeon/vcn/vp9: search the render target from the whole list</li>
</ul>
<p>Lionel Landwerlin (1):</p>
<ul>
<li>intel: add dependency on genxml generated files</li>
</ul>
<p>Marek Olšák (1):</p>
<ul>
<li>radeonsi: fix assertion failure by using the correct type</li>
</ul>
<p>Samuel Pitoiset (2):</p>
<ul>
<li>radv: skip updating depth/color metadata for conditional rendering</li>
<li>radv: do not always initialize HTILE in compressed state</li>
</ul>
</div>
</body>
</html>
......@@ -1258,7 +1258,7 @@ radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
++reg_count;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
......@@ -1282,7 +1282,7 @@ radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
uint64_t va = radv_buffer_get_va(image->bo);
va += image->offset + image->tc_compat_zrange_offset;
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
......@@ -1476,7 +1476,7 @@ radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
S_370_WR_CONFIRM(1) |
S_370_ENGINE_SEL(V_370_PFP));
......@@ -4407,8 +4407,14 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
return;
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
/* TODO: merge with the clear if applicable */
radv_initialize_htile(cmd_buffer, image, range, 0);
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
if (radv_layout_is_htile_compressed(image, dst_layout,
dst_queue_mask)) {
clear_value = 0;
}
radv_initialize_htile(cmd_buffer, image, range, clear_value);
} else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
......
......@@ -48,7 +48,6 @@
#include "util/build_id.h"
#include "util/debug.h"
#include "util/mesa-sha1.h"
#include "compiler/glsl_types.h"
static int
radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
......@@ -611,7 +610,6 @@ void radv_DestroyInstance(
VG(VALGRIND_DESTROY_MEMPOOL(instance));
_mesa_glsl_release_types();
_mesa_locale_fini();
vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
......
......@@ -820,8 +820,8 @@
<packet code="120" name="Tile Binning Mode Cfg" min_ver="41">
<field name="Height (in pixels)" size="12" start="48" type="uint" minus_one="true"/>
<field name="Width (in pixels)" size="12" start="32" type="uint" minus_one="true"/>
<field name="Height (in pixels)" size="16" start="48" type="uint" minus_one="true"/>
<field name="Width (in pixels)" size="16" start="32" type="uint" minus_one="true"/>
<field name="Double-buffer in non-ms mode" size="1" start="15" type="bool"/>
<field name="Multisample Mode (4x)" size="1" start="14" type="bool"/>
......
......@@ -32,7 +32,8 @@
*/
#define V3D_MAX_TEXTURE_SAMPLERS 16
#define V3D_MAX_MIP_LEVELS 12
/* The HW can do 16384 (15), but we run into hangs when we expose that. */
#define V3D_MAX_MIP_LEVELS 13
#define V3D_MAX_SAMPLES 4
......
......@@ -812,8 +812,8 @@ print_intrinsic_instr(nir_intrinsic_instr *instr, print_state *state)
assert(dim < ARRAY_SIZE(dim_name) && dim_name[dim]);
fprintf(fp, " image_dim=%s", dim_name[dim]);
} else if (idx == NIR_INTRINSIC_IMAGE_ARRAY) {
bool array = nir_intrinsic_image_dim(instr);
fprintf(fp, " image_dim=%s", array ? "true" : "false");
bool array = nir_intrinsic_image_array(instr);
fprintf(fp, " image_array=%s", array ? "true" : "false");
} else if (idx == NIR_INTRINSIC_DESC_TYPE) {
VkDescriptorType desc_type = nir_intrinsic_desc_type(instr);
fprintf(fp, " desc_type=%s", vulkan_descriptor_type_name(desc_type));
......
......@@ -77,6 +77,15 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
}
}
nir_foreach_if_use(src, def) {
nir_block *block_before_if =
nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
is_valid = false;
break;
}
}
if (is_valid)
return true;
......@@ -98,6 +107,15 @@ repair_ssa_def(nir_ssa_def *def, void *void_state)
}
}
nir_foreach_if_use_safe(src, def) {
nir_block *block_before_if =
nir_cf_node_as_block(nir_cf_node_prev(&src->parent_if->cf_node));
if (!nir_block_dominates(def->parent_instr->block, block_before_if)) {
nir_if_rewrite_condition(src->parent_if, nir_src_for_ssa(
nir_phi_builder_value_get_block_def(val, block_before_if)));
}
}
return true;
}
......
......@@ -64,6 +64,7 @@ static rvcn_dec_message_avc_t get_h264_msg(struct radeon_decoder *dec,
memset(&result, 0, sizeof(result));
switch (pic->base.profile) {
case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
case PIPE_VIDEO_PROFILE_MPEG4_AVC_CONSTRAINED_BASELINE:
result.profile = RDECODE_H264_PROFILE_BASELINE;
break;
......@@ -490,7 +491,7 @@ static rvcn_dec_message_vp9_t get_vp9_msg(struct radeon_decoder *dec,
assert(dec->base.max_references + 1 <= 16);
for (i = 0 ; i < dec->base.max_references + 1 ; ++i) {
for (i = 0 ; i < 16 ; ++i) {
if (dec->render_pic_list[i] && dec->render_pic_list[i] == target) {
result.curr_pic_idx =
(uintptr_t)vl_video_buffer_get_associated_data(target, &dec->base);
......
......@@ -186,7 +186,7 @@ static void si_emit_guardband(struct si_context *ctx)
ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
/* Indexed by quantization modes */
static unsigned max_viewport_size[] = {65535, 16383, 4095};
static int max_viewport_size[] = {65535, 16383, 4095};
/* Ensure that the whole viewport stays representable in
* absolute coordinates.
......
......@@ -491,7 +491,8 @@ v3d_tfu_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
if ((info->mask & PIPE_MASK_RGBA) == 0)
return false;
if (info->dst.box.x != 0 ||
if (info->scissor_enable ||
info->dst.box.x != 0 ||
info->dst.box.y != 0 ||
info->dst.box.width != dst_width ||
info->dst.box.height != dst_height ||
......
......@@ -185,7 +185,10 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return V3D_MAX_MIP_LEVELS;
if (screen->devinfo.ver < 40)
return 12;
else
return V3D_MAX_MIP_LEVELS;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 2048;
......
......@@ -55,7 +55,28 @@ v3d_start_draw(struct v3d_context *v3d)
job->submit.bcl_start = job->bcl.bo->offset;
v3d_job_add_bo(job, job->bcl.bo);
job->tile_alloc = v3d_bo_alloc(v3d->screen, 1024 * 1024, "tile_alloc");
/* The PTB will request the tile alloc initial size per tile at start
* of tile binning.
*/
uint32_t tile_alloc_size = (job->draw_tiles_x *
job->draw_tiles_y) * 64;
/* The PTB allocates in aligned 4k chunks after the initial setup. */
tile_alloc_size = align(tile_alloc_size, 4096);
/* Include the first two chunk allocations that the PTB does so that
* we definitely clear the OOM condition before triggering one (the HW
* won't trigger OOM during the first allocations).
*/
tile_alloc_size += 8192;
/* For performance, allocate some extra initial memory after the PTB's
* minimal allocations, so that we hopefully don't have to block the
* GPU on the kernel handling an OOM signal.
*/
tile_alloc_size += 512 * 1024;
job->tile_alloc = v3d_bo_alloc(v3d->screen, tile_alloc_size,
"tile_alloc");
uint32_t tsda_per_tile_size = v3d->screen->devinfo.ver >= 40 ? 256 : 64;
job->tile_state = v3d_bo_alloc(v3d->screen,
job->draw_tiles_y *
......
......@@ -846,6 +846,9 @@ v3d_setup_texture_shader_state(struct V3DX(TEXTURE_SHADER_STATE) *tex,
prsc->target == PIPE_TEXTURE_1D_ARRAY) {
tex->image_height = tex->image_width >> 14;
}
tex->image_width &= (1 << 14) - 1;
tex->image_height &= (1 << 14) - 1;
#endif
if (prsc->target == PIPE_TEXTURE_3D) {
......
......@@ -27,6 +27,19 @@
#include "va_private.h"
const int reverse_inverse_zscan[] =
{
/* Reverse inverse z scan pattern */
0, 2, 3, 9, 10, 20, 21, 35,
1, 4, 8, 11, 19, 22, 34, 36,
5, 7, 12, 18, 23, 33, 37, 48,
6, 13, 17, 24, 32, 38, 47, 49,
14, 16, 25, 31, 39, 46, 50, 57,
15, 26, 30, 40, 45, 51, 56, 58,
27, 29, 41, 44, 52, 55, 59, 62,
28, 42, 43, 53, 54, 60, 61, 63,
};
void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *context, vlVaBuffer *buf)
{
VAPictureParameterBufferMPEG2 *mpeg2 = buf->data;
......@@ -66,16 +79,29 @@ void vlVaHandlePictureParameterBufferMPEG12(vlVaDriver *drv, vlVaContext *contex
void vlVaHandleIQMatrixBufferMPEG12(vlVaContext *context, vlVaBuffer *buf)
{
VAIQMatrixBufferMPEG2 *mpeg2 = buf->data;
static uint8_t temp_intra_matrix[64];
static uint8_t temp_nonintra_matrix[64];
assert(buf->size >= sizeof(VAIQMatrixBufferMPEG2) && buf->num_elements == 1);
if (mpeg2->load_intra_quantiser_matrix)
context->desc.mpeg12.intra_matrix = mpeg2->intra_quantiser_matrix;
else
if (mpeg2->load_intra_quantiser_matrix) {
/* The quantiser matrix that VAAPI provides has been applied
with inverse z-scan. However, what we expect in MPEG2
picture description is the original order. Therefore,
we need to reverse it back to its original order.
*/
for (int i = 0; i < 64; i++)
temp_intra_matrix[i] =
mpeg2->intra_quantiser_matrix[reverse_inverse_zscan[i]];
context->desc.mpeg12.intra_matrix = temp_intra_matrix;
} else
context->desc.mpeg12.intra_matrix = NULL;
if (mpeg2->load_non_intra_quantiser_matrix)
context->desc.mpeg12.non_intra_matrix = mpeg2->non_intra_quantiser_matrix;
else
if (mpeg2->load_non_intra_quantiser_matrix) {
for (int i = 0; i < 64; i++)
temp_nonintra_matrix[i] =
mpeg2->non_intra_quantiser_matrix[reverse_inverse_zscan[i]];
context->desc.mpeg12.non_intra_matrix = temp_nonintra_matrix;
} else
context->desc.mpeg12.non_intra_matrix = NULL;
}
......
......@@ -60,6 +60,9 @@ libgallium_dri = shared_library(
driver_tegra, driver_i915, driver_svga, driver_virgl,
driver_swr,
],
# Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : dri_drivers_path,
)
foreach d : [[with_gallium_kmsro, 'pl111_dri.so'],
......
......@@ -49,6 +49,7 @@ libva_gallium = shared_library(
dep_libdrm, dep_thread, driver_r600, driver_radeonsi, driver_nouveau,
],
link_depends : va_link_depends,
# Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : va_drivers_path,
)
......
......@@ -55,6 +55,9 @@ libvdpau_gallium = shared_library(
],
link_depends : vdpau_link_depends,
soversion : '@0@.@1@.0'.format(VDPAU_MAJOR, VDPAU_MINOR),
# Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : vdpau_drivers_path,
)
foreach d : [[with_gallium_r300, 'r300'],
[with_gallium_r600, 'r600'],
......
......@@ -47,6 +47,9 @@ libxvmc_gallium = shared_library(
],
dependencies : [dep_thread, driver_r600, driver_nouveau],
link_depends : xvmc_link_depends,
# Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : xvmc_drivers_path,
)
foreach d : [[with_gallium_r600, 'r600'], [with_gallium_nouveau, 'nouveau']]
......
......@@ -642,7 +642,6 @@ dri3_set_swap_interval(__GLXDRIdrawable *pdraw, int interval)
break;
}
priv->swap_interval = interval;
loader_dri3_set_swap_interval(&priv->loader_drawable, interval);
return 0;
......@@ -659,7 +658,7 @@ dri3_get_swap_interval(__GLXDRIdrawable *pdraw)
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
return priv->swap_interval;
return priv->loader_drawable.swap_interval;
}
static void
......
......@@ -117,7 +117,6 @@ struct dri3_context
struct dri3_drawable {
__GLXDRIdrawable base;
struct loader_dri3_drawable loader_drawable;
int swap_interval;
/* LIBGL_SHOW_FPS support */
uint64_t previous_ust;
......
......@@ -33,5 +33,5 @@ libblorp = static_library(
files_libblorp,
include_directories : [inc_common, inc_intel],
c_args : [c_vis_args, no_override_init_args],
dependencies : idep_nir_headers,
dependencies : [idep_nir_headers, idep_genxml],
)
......@@ -43,5 +43,5 @@ libintel_common = static_library(
include_directories : [inc_common, inc_intel],
c_args : [c_vis_args, no_override_init_args],
link_with : [libisl],
dependencies : [dep_expat, dep_libdrm, dep_thread],
dependencies : [dep_expat, dep_libdrm, dep_thread, idep_genxml],
)
......@@ -57,3 +57,5 @@ foreach f : gen_xml_files
capture : true,
)
endforeach
idep_genxml = declare_dependency(sources : [gen_xml_pack, genX_bits_h, genX_xml_h])
......@@ -21,9 +21,9 @@
c_sse2_args = ['-msse2', '-mstackrealign']
inc_intel = include_directories('.')
subdir('genxml')
subdir('blorp')
subdir('dev')
subdir('genxml')
subdir('isl')
subdir('common')
subdir('compiler')
......
......@@ -41,7 +41,6 @@
#include "git_sha1.h"
#include "vk_util.h"
#include "common/gen_defines.h"
#include "compiler/glsl_types.h"
#include "genxml/gen7_pack.h"
......@@ -704,7 +703,6 @@ void anv_DestroyInstance(
vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
_mesa_glsl_release_types();
_mesa_locale_fini();
vk_free(&instance->alloc, instance);
......
......@@ -203,7 +203,7 @@ libvulkan_intel = shared_library(
libvulkan_util, libvulkan_wsi, libmesa_util,
],
dependencies : [
dep_thread, dep_dl, dep_m, anv_deps, idep_nir,
dep_thread, dep_dl, dep_m, anv_deps, idep_nir, idep_genxml,
],
c_args : anv_flags,
link_args : ['-Wl,--build-id=sha1', ld_args_bsymbolic, ld_args_gc_sections],
......
......@@ -187,7 +187,7 @@ libi965 = static_library(
i965_gen_libs, libintel_common, libintel_dev, libisl, libintel_compiler,
libblorp
],
dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers],
dependencies : [dep_libdrm, dep_valgrind, idep_nir_headers, idep_genxml],
)
dri_drivers += libi965
......
......@@ -54,6 +54,9 @@ if dri_drivers != []
dep_selinux, dep_libdrm, dep_expat, dep_m, dep_thread, dep_dl, idep_nir,
],
link_args : [ld_args_build_id, ld_args_bsymbolic, ld_args_gc_sections],
# Will be deleted during installation, see install_megadrivers.py
install : true,
install_dir : dri_drivers_path,
)
meson.add_install_script(
......