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Commit 2b43464c authored by Wilson Snyder's avatar Wilson Snyder
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Verilog-Perl: `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish)

git-svn-id: file://localhost/svn/Verilog-Perl/trunk/Verilog-Perl@77442 c99bdd1b-02e9-0310-b855-c9df8d5cb90a
parent c6f28ad6
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......@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilog::Language 3.2****
*** `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish).
*** Fix parsing class member variables with multiple qualifiers.
**** Fix Netlist errors with ported interfaces, bug86. [David A]
......
......@@ -93,8 +93,10 @@ drop [\032]
/* Optional directives we recognize */
<INITIAL>"`__FILE__" { if (!pedantic()) {
yytext = (char*)VPreprocLex::s_currentLexp->m_curFilelinep->cfilename();
yyleng = strlen(yytext); return (VP_TEXT);
static string rtnfile;
rtnfile = '"'; rtnfile += VPreprocLex::s_currentLexp->m_curFilelinep->cfilename();
rtnfile += '"'; yytext=(char*)rtnfile.c_str(); yyleng = rtnfile.length();
return (VP_STRING);
} else return(VP_DEFREF); }
<INITIAL>"`__LINE__" { if (!pedantic()) {
static char buf[10];
......
......@@ -4,7 +4,7 @@ verilog/inc2.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:2: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:3: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc2.v:4: At file verilog/inc2.v line 4
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc3.v:1:
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
......@@ -17,7 +17,7 @@ inc3_a_filename_from_line_directive:6:
inc3_a_filename_from_line_directive:7:
inc3_a_filename_from_line_directive:8:
inc3_a_filename_from_line_directive:9: // FOO
inc3_a_filename_from_line_directive:10: At file inc3_a_filename_from_line_directive line 10
inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:11:
inc3_a_filename_from_line_directive:12:
inc3_a_filename_from_line_directive:13:
......
......@@ -13,11 +13,11 @@ verilog/inc_ifdef.v:26: `line 26 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:40: `line 40 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:41: `line 41 "verilog/inc_ifdef.v" 2
verilog/inc_ifdef.v:41: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:4: At file verilog/inc2.v line 4
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:10: At file inc3_a_filename_from_line_directive line 10
inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:13: `line 13 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:17: `line 17 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:18: `line 18 "inc3_a_filename_from_line_directive" 2
......
......@@ -58,7 +58,7 @@ verilog/inc_ifdef.v:41: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:1: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:2: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:3: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc2.v:4: At file verilog/inc2.v line 4
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc3.v:1:
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
......@@ -71,7 +71,7 @@ inc3_a_filename_from_line_directive:6:
inc3_a_filename_from_line_directive:7:
inc3_a_filename_from_line_directive:8:
inc3_a_filename_from_line_directive:9: // FOO
inc3_a_filename_from_line_directive:10: At file inc3_a_filename_from_line_directive line 10
inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:11:
inc3_a_filename_from_line_directive:12:
inc3_a_filename_from_line_directive:13:
......
......@@ -64,7 +64,7 @@ COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:2: /*CMT*/
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc2.v:3: /*CMT*/
verilog/inc2.v:4: At file verilog/inc2.v line 4
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc3.v:1:
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
......@@ -81,7 +81,7 @@ inc3_a_filename_from_line_directive:7:
inc3_a_filename_from_line_directive:8:
COMMENT: // FOO
inc3_a_filename_from_line_directive:9: /*CMT*/
inc3_a_filename_from_line_directive:10: At file inc3_a_filename_from_line_directive line 10
inc3_a_filename_from_line_directive:10: At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:11:
inc3_a_filename_from_line_directive:12:
inc3_a_filename_from_line_directive:13:
......
......@@ -538,4 +538,4 @@ verilog/parser_sv.v:231: ENDTASKFUNC 'endfunction'
verilog/parser_sv.v:235: TASK 'task' 'do_reset'
verilog/parser_sv.v:235: PORT 'kind' 'task' '' 'vmm_cl_func_colon::restart_e' '' '1'
verilog/parser_sv.v:238: TASK 'task' 'empty_comma'
verilog/parser_sv.v:243: ENDTASKFUNC 'endtask'
verilog/parser_sv.v:244: ENDTASKFUNC 'endtask'
......@@ -2,7 +2,7 @@
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2009 by Wilson Snyder.
At file verilog/inc2.v line 4
At file "verilog/inc2.v" line 4
`line 5 "verilog/inc2.v" 0
`line 1 "verilog/inc3.v" 1
......@@ -15,7 +15,7 @@ At file verilog/inc2.v line 4
// FOO
At file inc3_a_filename_from_line_directive line 10
At file "inc3_a_filename_from_line_directive" line 10
......
At file verilog/inc2.v line 4
At file inc3_a_filename_from_line_directive line 10
At file "verilog/inc2.v" line 4
At file "inc3_a_filename_from_line_directive" line 10
......@@ -240,4 +240,5 @@ task empty_comma;
extracomma2("a",);
extracomma3("a",,"c");
extracomma4(,"b");
file_is_a_string(`__FILE__,`__LINE__);
endtask
......@@ -1086,7 +1086,7 @@ sub symbol {
my $since = $parser->unreadback(); $parser->unreadback('');
if ($token eq "__LINE__") { $token = $parser->lineno(); }
if ($token eq "__FILE__") { $token = $parser->filename(); }
if ($token eq "__FILE__") { $token = '"'.$parser->filename().'"'; }
if ($In_Message) {
$Params[$Param_Num] .= $since . $token;
......
......@@ -214,9 +214,9 @@ The following additional constructs may be added to your Verilog code.
=item `__FILE__
The __FILE__ define expands to the current filename, like C++'s __FILE__.
This is in the draft SystemVerilog 2009 standard (but supported by
Verilog-Perl since 2004!)
The __FILE__ define expands to the current filename as a string, like C++'s
__FILE__. This is in the draft SystemVerilog 2009 standard (but supported
by Verilog-Perl since 2004!)
=item `__LINE__
......
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