Verilog-Perl: Fix endclass keyword

git-svn-id: file://localhost/svn/Verilog-Perl/trunk/Verilog-Perl@48220 c99bdd1b-02e9-0310-b855-c9df8d5cb90a

Changes

@@ -3,6 +3,10 @@ Revision history for Perl extension Verilog::Language.
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilog::Language 3.02***
+
+****	Fix endclass keyword parsing.  [David Plumb]
+
 * Verilog::Language 3.020 2007/12/03
 
 **	Add SystemVerilog logic types.  [Thomas Ziller]

Parser/VParseLex.l

@@ -285,7 +285,7 @@ escid	\\[^ \t\f\r\n]+
   "coverpoint"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
   "cross"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
   "dist"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
-  "endcass"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
+  "endclass"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
   "endclocking"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
   "endgroup"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }
   "endpackage"		{ FL; VALTEXT; CALLBACK(keywordCb); return ygenKEYWORD; }