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Commit 54c5087d authored by Wilson Snyder's avatar Wilson Snyder
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Fix vhier infinite loop on recursive modules.

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......@@ -8,6 +8,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Add Parser useProtected argument to aid runtime, bug899. [Corey Teffetalor]
**** Fix vhier infinite loop on recursive modules.
* Verilog::Language 3.412 2015-03-16
......
......@@ -162,6 +162,7 @@ verilog/v_hier_subprim.v
verilog/v_hier_subsub.v
verilog/v_hier_top.v
verilog/v_hier_top2.v
verilog/v_recursive.v
verilog/v_sv_intf.v
verilog/v_sv_mod.v
verilog/v_sv_pgm.v
......
......@@ -52,6 +52,7 @@ is_deeply (\@mods, ['$root',
'v_sv_pgm',
'v_hier_sub',
'v_hier_top2',
'v_recursive',
'v_hier_top',
'v_sv_mod']);
......
......@@ -38,6 +38,7 @@ ok(1, "use");
#$nl->lint(); # Optional, see docs; probably not wanted
$nl->exit_if_error();
my %recursing; # Prevent recursion; not in example
foreach my $mod ($nl->top_modules_sorted) {
show_hier ($mod, " ", "", "");
}
......@@ -47,6 +48,8 @@ ok(1, "use");
my $indent = shift;
my $hier = shift;
my $cellname = shift;
return if ++$recursing{$mod->name};
++$recursing{$mod->name}; # Not in example
if (!$cellname) {$hier = $mod->name;} #top modules get the design name
else {$hier .= ".$cellname";} #append the cellname
printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
......@@ -60,6 +63,7 @@ ok(1, "use");
}
show_hier ($cell->submod, $indent." ", $hier, $cell->name) if $cell->submod;
}
--$recursing{$mod->name}; # Not in example
}
print "Dump\n";
......
......@@ -62,6 +62,8 @@ Module:v_hier_top Kwd:module File:verilog/v_hier_top.v
Net:asn_clk DeclT:net NetT:wire DataT: Array:
Net:clk O DeclT:port NetT: DataT: Array:
Cell:missing is-a:missing
Cell:recursive is-a:v_recursive .DEPTH(3)
Module:v_recursive Kwd:module File:verilog/v_recursive.v
Cell:sub is-a:v_hier_sub
Module:v_hier_sub Kwd:module File:verilog/v_hier_sub.v
Pin:avec Net:{avec[3],avec[2:0]}
......@@ -79,3 +81,7 @@ Module:v_hier_top2 Kwd:module File:verilog/v_hier_top2.v
Net:iosig DeclT:port NetT: DataT:[2:0] Array: 2:0
Cell:noport is-a:v_hier_noport
Module:v_hier_noport Kwd:module File:verilog/v_hier_noport.v
Module:v_recursive Kwd:module File:verilog/v_recursive.v
Net:DEPTH DeclT:parameter NetT: DataT: Array: Value:1
Cell:recurse is-a:v_recursive .DEPTH(DEPTH-1)
Module:v_recursive Kwd:module File:verilog/v_recursive.v
v_hier_top
v_recursive
v_hier_sub
v_hier_subsub
v_hier_subsub
v_hier_top v_hier_top
|--recursive v_recursive
\--sub v_hier_sub
|--subsub0 v_hier_subsub
\--subsub2 v_hier_subsub
verilog/v_hier_sub.v
verilog/v_hier_subsub.v
verilog/v_hier_top.v
verilog/v_recursive.v
verilog/v_hier_top.v
verilog/v_hier_sub.v
verilog/v_recursive.v
verilog/v_hier_subsub.v
<vhier>
<cells>
<cell name="v_hier_top" submodname="v_hier_top" hier="v_hier_top">
<cell name="recursive" submodname="v_recursive" hier="v_hier_top.recursive">
</cell>
<cell name="sub" submodname="v_hier_sub" hier="v_hier_top.sub">
<cell name="subsub0" submodname="v_hier_subsub" hier="v_hier_top.sub.subsub0">
</cell>
......@@ -12,12 +14,14 @@
<module_files>
<file>verilog/v_hier_top.v</file>
<file>verilog/v_hier_sub.v</file>
<file>verilog/v_recursive.v</file>
<file>verilog/v_hier_subsub.v</file>
</module_files>
<input_files>
<file>verilog/v_hier_sub.v</file>
<file>verilog/v_hier_subsub.v</file>
<file>verilog/v_hier_top.v</file>
<file>verilog/v_recursive.v</file>
</input_files>
<missing_modules>
<module name="missing" />
......
......@@ -20,6 +20,8 @@ module v_hier_top (/*AUTOARG*/
missing missing ();
v_recursive #(.DEPTH(3)) recursive ();
// Width checks, bug65
wire WC_w1;
wire [0:0] WC_w1b;
......
module v_recursive ();
parameter DEPTH = 1;
generate
if (DEPTH > 1) begin : rec
v_recursive #(.DEPTH(DEPTH-1)) recurse ();
end
endgenerate
endmodule
......@@ -168,7 +168,8 @@ sub vhier {
$fh->print(" <cells>\n") if $Opt_Xml;
foreach my $mod ($nl->modules_sorted) {
if ($mod->is_top) {
show_hier ($fh, $mod, undef, " ", $mod->name);
my %recursing;
show_hier ($fh, \%recursing, $mod, undef, " ", $mod->name);
}
}
$fh->print(" </cells>\n") if $Opt_Xml;
......@@ -240,7 +241,8 @@ sub show_mod_files {
# Recurse the tree and determine level
foreach my $mod ($nl->modules, $nl->interfaces) {
if ($mod->is_top) {
_mod_files_recurse($mod, 1);
my %recursing;
_mod_files_recurse($mod, 1, \%recursing);
}
}
# Make sort key based on numeric level
......@@ -272,7 +274,7 @@ sub _mod_mark_recurse {
my $mod = shift;
my $marked = shift;
$marked->{$mod->name} = 1;
return if $marked->{$mod->name}++;
foreach my $cell ($mod->cells_sorted) {
if ($cell->submod) {
_mod_mark_recurse ($nl, $cell->submod, $marked);
......@@ -283,18 +285,25 @@ sub _mod_mark_recurse {
sub _mod_files_recurse {
my $mod = shift;
my $level = shift;
my $recursing = shift;
my $name = $mod->name;
return if $recursing->{$name};
++$recursing->{$name};
if (($mod->attributes("_vhier_level")||0) < $level) {
$mod->attributes("_vhier_level", $level);
}
foreach my $cell ($mod->cells_sorted) {
if ($cell->submod) {
_mod_files_recurse ($cell->submod, $level+1);
_mod_files_recurse ($cell->submod, $level+1, $recursing);
}
}
--$recursing->{$name};
}
sub show_hier {
my $fh = shift;
my $recursing = shift;
my $mod = shift;
my $parcell = shift;
my $indent = shift;
......@@ -302,23 +311,26 @@ sub show_hier {
my $submodname = shift;
# print the design hierarchy starting at mod (recursive)
printf "%-38s %s\n", $indent."Module ".$mod->name,$hier if $Debug;
my $instance = $parcell ? $parcell->name : $mod->name;
my $name = $mod->name;
return if $recursing->{$name};
++$recursing->{$name};
printf "%-38s %s\n", $indent."Module ".$name,$hier if $Debug;
my $instance = $parcell ? $parcell->name : $name;
# print the mod instance
$Opt_Xml ?
$fh->printf("%s<cell name=\"%s\" submodname=\"%s\" hier=\"%s\">\n",
$indent, $parcell ? $parcell->name : $mod->name, $mod->name, $hier) :
$indent, $parcell ? $parcell->name : $name, $name, $hier) :
$Opt_Instance ?
$fh->printf("%s%s %s\n", $indent, $instance, $mod->name) :
$fh->printf("%s%s\n", $indent, $mod->name);
$fh->printf("%s%s %s\n", $indent, $instance, $name) :
$fh->printf("%s%s\n", $indent, $name);
# print the design hierarchy of each cell in mod
my $i = 0;
my $suffix;
my @cellCount = $mod->cells_sorted; # Returns list of name sorted references to Verilog::Netlist::Cell in the module
$fh->printf("\t\t%d cells_sorted for %s\n", $#cellCount+1, $mod->name) if $Debug;
$fh->printf("\t\t%d cells_sorted for %s\n", $#cellCount+1, $name) if $Debug;
my @subMods = grep($_->submod, $mod->cells_sorted); # list of submods of the current mod
......@@ -340,11 +352,12 @@ sub show_hier {
} else {
$suffix = " "; # simple indenting with spaces
}
show_hier ($fh, $cell->submod, $cell, $indent.$suffix, $hier.".".$cell->name);
show_hier ($fh, $recursing, $cell->submod, $cell, $indent.$suffix, $hier.".".$cell->name);
$i++;
}
}
$fh->printf("%s</cell>\n", $indent) if $Opt_Xml;
--$recursing->{$name};
}
######################################################################
......
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