Verilog-Perl: Fix Preprocessor dropping some line directives

git-svn-id: file://localhost/svn/Verilog-Perl/trunk/Verilog-Perl@40354 c99bdd1b-02e9-0310-b855-c9df8d5cb90a

Changes

@@ -3,6 +3,10 @@ Revision history for Perl extension Verilog::Language.
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilog::Language 3.00***
+
+****	Fix Preprocessor dropping some `line directives.  [Mark Nodine]
+
 * Verilog::Language 3.000 2007/06/12
 
 ** 	Note this is a MAJOR release that may have incompatibilities with

Preproc/src/VPreproc.cpp

@@ -175,6 +175,7 @@ const char* VPreprocImp::tokenName(int tok) {
     case VP_DEFINE	: return("DEFINE");
     case VP_ELSE	: return("ELSE");	
     case VP_ELSIF	: return("ELSIF");	
+    case VP_LINE	: return("LINE");	
     case VP_SYMBOL	: return("SYMBOL");
     case VP_STRING	: return("STRING");
     case VP_DEFVALUE	: return("DEFVALUE");
@@ -431,6 +432,10 @@ int VPreprocImp::getToken() {
 	    for (int len=0; len<yyleng; len++) { if (yytext[len]=='\n') m_lineAdd++; }
 	    goto next_tok;
 	}
+	if (tok==VP_LINE) {
+	    addLineComment(0);
+	    goto next_tok;
+	}
 	// Deal with some special parser states
 	switch (m_state) {
 	case ps_TOP: {

Preproc/src/VPreprocLex.h

@@ -41,6 +41,7 @@
 #define VP_DEFINE	261
 #define VP_ELSE		262
 #define VP_ELSIF	263
+#define VP_LINE		264
 
 #define VP_SYMBOL	300
 #define VP_STRING	301

Preproc/src/VPreprocLex.l

@@ -64,7 +64,8 @@ drop		[\032]
 	/**************************************************************/
 %%
 
-<INITIAL>^{ws}*"`line"{ws}+.*{crnl}	{ VPreprocLex::s_currentLexp->lineDirective(yytext); }
+<INITIAL>^{ws}*"`line"{ws}+.*{crnl}	{ VPreprocLex::s_currentLexp->lineDirective(yytext);
+					  return(VP_LINE); }
 
 	/* Special directives we recognise */
 <INITIAL>"`include"	{ return(VP_INCLUDE); }

t/30_preproc.out

@@ -12,6 +12,8 @@ verilog/inc3.v:1:
 verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
 verilog/inc3.v:1: 
 verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
+verilog/inc3.v:1: 
+verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
 inc3_a_filename_from_line_directive:2: // DESCRIPTION: Verilog::Preproc: Example source code
 inc3_a_filename_from_line_directive:3: // This file ONLY is placed into the Public Domain, for any use,
 inc3_a_filename_from_line_directive:4: // without warranty, 2000-2007 by Wilson Snyder.

t/30_preproc_nows.out

@@ -4,6 +4,7 @@ verilog/inc2.v:1: `line 1 "verilog/inc2.v" 1
 verilog/inc2.v:4: At file verilog/inc2.v line 4
 verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
 verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
+verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
 inc3_a_filename_from_line_directive:10:  At file inc3_a_filename_from_line_directive line 10
 inc3_a_filename_from_line_directive:13: `line 13 "inc3_a_filename_from_line_directive" 0
 inc3_a_filename_from_line_directive:17: `line 17 "inc3_a_filename_from_line_directive" 0

t/30_preproc_on.out

@@ -12,6 +12,8 @@ verilog/inc3.v:1:
 verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
 verilog/inc3.v:1: 
 verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
+verilog/inc3.v:1: 
+verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
 inc3_a_filename_from_line_directive:2: // DESCRIPTION: Verilog::Preproc: Example source code
 inc3_a_filename_from_line_directive:3: // This file ONLY is placed into the Public Domain, for any use,
 inc3_a_filename_from_line_directive:4: // without warranty, 2000-2007 by Wilson Snyder.

t/30_preproc_sub.out

@@ -15,6 +15,8 @@ verilog/inc3.v:1:
 verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
 verilog/inc3.v:1: 
 verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
+verilog/inc3.v:1: 
+verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
 COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
 inc3_a_filename_from_line_directive:2:  /*CMT*/ 
 COMMENT: // This file ONLY is placed into the Public Domain, for any use,

t/80_vppp.t

@@ -15,16 +15,16 @@ BEGIN { require "t/test_utils.pl"; }
 
 print "Checking vppp...\n";
 
-vppp ("t/80_vppp_none.out",   "");
-vppp ("t/80_vppp_cmped.out", "--nocomment --pedantic");
-vppp ("t/80_vppp_simple.out", "--simple");
+vppp ("t/80_vppp_none.out",   "test_dir/vppp_none.v",	"");
+vppp ("t/80_vppp_cmped.out",  "test_dir/vppp_cmped.v",	"--nocomment --pedantic");
+vppp ("t/80_vppp_simple.out", "test_dir/vppp_simple.v",	"--simple");
 
 sub vppp {
     my $checkname = shift;
+    my $out = shift;
     my $flags = shift;
 
-    my $out = "test_dir/vppp.v";
     run_system ("${PERL} vppp ${flags} -y verilog inc2.v > $out");
     ok(-r $out);
-    ok(files_identical ($checkname, $out));
+    ok(files_identical ($out, $checkname));
 }

t/80_vppp_cmped.out

@@ -9,6 +9,8 @@ At file `__FILE__  line `__LINE__
 
 `line 1 "verilog/inc3.v" 1
 
+`line 2 "inc3_a_filename_from_line_directive" 0
+
 
 
 

t/80_vppp_none.out

@@ -8,6 +8,8 @@ At file verilog/inc2.v  line 4
 `line 5 "verilog/inc2.v" 0
 
 `line 1 "verilog/inc3.v" 1
+
+`line 2 "inc3_a_filename_from_line_directive" 0
 // DESCRIPTION: Verilog::Preproc: Example source code
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2000-2007 by Wilson Snyder.