Fixed code to be Perl::Critic clean.

git-svn-id: file://localhost/svn/Verilog-Perl/trunk/Verilog-Perl@60212 c99bdd1b-02e9-0310-b855-c9df8d5cb90a

Changes

@@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks!
 	Verilog::Netlist::Logger class.  This allows errors to be caught or
 	specially handled.  [Miguel Corazao, AMD]
 
+****	Fixed code to be Perl::Critic clean.
+
 * Verilog::Language 3.040 2008/08/20
 
 ***	Add Netlist::Net->value containing parameter values.  [Ron D Smith]

Getopt.pm

@@ -300,7 +300,7 @@ sub write_parameters_file {
 # Utility functions
 
 sub remove_duplicates {
-    my $self = shift if ref $_[0];
+    my $self = ref $_[0] && shift;
     # return list in same order, with any duplicates removed
     my @rtn;
     my %hit;

Language.pm

@@ -384,9 +384,8 @@ sub number_value {
     }
     elsif ($number =~ /\'s?b([0-1]+)$/i) {
 	my $val = 0;
-	my $bit;
 	$number = $1;
-	foreach $bit (split(//, $number)) {
+	foreach my $bit (split(//, $number)) {
 	    $val = ($val<<1) | ($bit=='1'?1:0);
 	}
 	return ($val);

MANIFEST

@@ -18,11 +18,11 @@ Netlist/Pin.pm
 Netlist/Port.pm
 Netlist/Subclass.pm
 Parser/.gitignore
+Parser/bisonpre
 Parser/Makefile.PL
 Parser/Parser.pm
 Parser/Parser.xs
 Parser/SigParser.pm
-Parser/bisonpre
 Parser/typemap
 Parser/VParse.cpp
 Parser/VParse.h
@@ -48,6 +48,7 @@ t/00_pod.t
 t/01_manifest.t
 t/02_help.t
 t/03_spaces.t
+t/04_critic.t
 t/10_keywords.t
 t/12_splitbus.t
 t/14_numbers.t

Netlist.pm

@@ -19,7 +19,7 @@ use IO::File;
 use Verilog::Netlist::Module;
 use Verilog::Netlist::File;
 use Verilog::Netlist::Subclass;
-@ISA = qw(Verilog::Netlist::Subclass);
+use base qw(Verilog::Netlist::Subclass);
 use strict;
 use vars qw($Debug $Verbose $VERSION);
 

Netlist/Cell.pm

@@ -17,10 +17,12 @@ use Class::Struct;
 
 use Verilog::Netlist;
 use Verilog::Netlist::Subclass;
+use vars qw($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::Cell::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 structs('new',
 	'Verilog::Netlist::Cell::Struct'

Netlist/File.pm

@@ -18,10 +18,12 @@ use Carp;
 
 use Verilog::Netlist;
 use Verilog::Netlist::Subclass;
+use vars qw($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::File::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 structs('new',
 	'Verilog::Netlist::File::Struct'
@@ -43,9 +45,8 @@ structs('new',
 package Verilog::Netlist::File::Parser;
 use Verilog::SigParser;
 use Verilog::Preproc;
+use base qw (Verilog::SigParser);
 use strict;
-use vars qw (@ISA);
-@ISA = qw (Verilog::SigParser);
 
 sub new {
     my $class = shift;

Netlist/Logger.pm

@@ -14,9 +14,11 @@
 
 package Verilog::Netlist::Logger;
 require Exporter;
-$VERSION = '3.035';
+use vars qw($VERSION);
 use strict;
 
+$VERSION = '3.035';
+
 # We don't use Verilog::Netlist::Subclass, as this is called from it!
 
 ######################################################################

Netlist/Module.pm

@@ -21,10 +21,12 @@ use Verilog::Netlist::Net;
 use Verilog::Netlist::Cell;
 use Verilog::Netlist::Pin;
 use Verilog::Netlist::Subclass;
+use vars qw($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::Module::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 structs('new',
 	'Verilog::Netlist::Module::Struct'

Netlist/Net.pm

@@ -17,10 +17,12 @@ use Class::Struct;
 
 use Verilog::Netlist;
 use Verilog::Netlist::Subclass;
+use vars qw ($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::Net::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 ######################################################################
 

Netlist/Pin.pm

@@ -22,10 +22,12 @@ use Verilog::Netlist::Cell;
 use Verilog::Netlist::Module;
 use Verilog::Netlist::Pin;
 use Verilog::Netlist::Subclass;
+use vars qw($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::Pin::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 structs('new',
 	'Verilog::Netlist::Pin::Struct'

Netlist/Port.pm

@@ -17,10 +17,12 @@ use Class::Struct;
 
 use Verilog::Netlist;
 use Verilog::Netlist::Subclass;
+use vars qw($VERSION @ISA);
+use strict;
 @ISA = qw(Verilog::Netlist::Port::Struct
 	Verilog::Netlist::Subclass);
+
 $VERSION = '3.041';
-use strict;
 
 structs('new',
 	'Verilog::Netlist::Port::Struct'

Netlist/Subclass.pm

@@ -16,10 +16,12 @@ package Verilog::Netlist::Subclass;
 use Verilog::Netlist::Logger;
 use Class::Struct;
 require Exporter;
+use base qw(Exporter);
+use vars qw($VERSION @EXPORT);
+use strict;
+
 $VERSION = '3.041';
-@ISA = qw(Exporter);
 @EXPORT = qw(structs);
-use strict;
 
 # Maybe in the future.  For now all users of this must do it themselves
 #struct ('Verilog::Netlist::Subclass'
@@ -146,9 +148,9 @@ Verilog::Netlist::Subclass - Common routines for all classes
 
 =head1 SYNOPSIS
 
-  use Verilog::Netlist::Subclass;
   package Verilog::Netlist::Something;
-  @ISA = qw(Verilog::Netlist::Subclass);
+  use Verilog::Netlist::Subclass;
+  use base qw(Verilog::Netlist::Subclass);
 
   ...
 

Parser/Parser.pm

@@ -17,7 +17,7 @@ use Verilog::Getopt;
 use Verilog::Language;
 
 require DynaLoader;
-@ISA = qw(DynaLoader);
+use base qw(DynaLoader);
 
 use strict;
 use vars qw($VERSION $Debug);

Preproc/Preproc.pm

@@ -16,8 +16,7 @@ use Carp;
 use Verilog::Getopt;
 
 require DynaLoader;
-@ISA = qw(DynaLoader);
-
+use base qw(DynaLoader);
 use strict;
 use vars qw($VERSION);
 

t/04_critic.t

+#!/usr/bin/perl -w
+# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
+#
+# Copyright 2000-2008 by Wilson Snyder.  This program is free software;
+# you can redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+use strict;
+use Test;
+use warnings;
+
+eval { use Test::Perl::Critic; };
+if ($@) {
+    plan tests => 1;
+    skip("Test::Perl::Critic not installed so ignoring check (harmless)",1);
+} elsif (!$ENV{VERILATOR_AUTHOR_SITE}) {
+    plan tests => 1;
+    skip("author only test (harmless)",1);
+} else {
+    #-profile => "t/04_critic.rc"
+    Test::Perl::Critic->import( -verbose=>9,
+				-exclude=>['ProhibitExplicitReturnUndef',
+					   'ProhibitStringyEval'],
+	);
+    all_critic_ok();
+}

t/30_preproc.t

@@ -15,10 +15,11 @@ BEGIN { require "t/test_utils.pl"; }
 #######################################################################
 package MyPreproc;
 use Verilog::Preproc;
-use vars qw (@ISA);
-@ISA = qw(Verilog::Preproc);
+use base qw(Verilog::Preproc);
+
 sub comment { print $::OUTTO "COMMENT: $_[1]\n";
 	      $_[0]->unreadback(' /*CMT*/ '); }
+
 package main;
 #######################################################################
 

t/35_sigparser.t

@@ -16,8 +16,7 @@ BEGIN { require "t/test_utils.pl"; }
 package MyParser;
 use Verilog::SigParser;
 use strict;
-use vars qw(@ISA);
-@ISA = qw(Verilog::SigParser);
+use base qw(Verilog::SigParser);
 
 sub _common {
     my $self = shift;

t/36_sigmany.t

@@ -21,8 +21,7 @@ our $Any_Error;
 package MyParser;
 use Verilog::SigParser;
 use strict;
-use vars qw(@ISA);
-@ISA = qw(Verilog::SigParser);
+use base qw(Verilog::SigParser);
 
 sub _common {
 }

vpm

@@ -22,7 +22,9 @@ use FindBin qw($RealBin);
 use File::Copy;
 use strict "vars";
 
-use lib "$RealBin/..";
+use lib 'blib/arch';
+use lib 'blib/lib';
+use lib '.';
 use Verilog::Parser;
 use Verilog::Getopt;
 
@@ -218,8 +220,9 @@ sub assert_req_ack {
     ($req && $ack) or die "%Error: ".$Last_Parser->fileline.": Format of \$assert_req_ack boggled.\n";
     @params = map {
 	my $ipar = $_;
-	$_ = check_signame($_);
-	($_) or die "%Error: ".$Last_Parser->fileline.": Parameter $ipar isn't a signal\n";
+	$ipar = check_signame($ipar);
+	($ipar) or die "%Error: ".$Last_Parser->fileline.": Parameter $ipar isn't a signal\n";
+	$ipar;
     } @params;
 
     # Form new variables
@@ -378,8 +381,8 @@ sub message_write {
     my $par = $params[2];
     $par =~ s/^\s*\"//;
     sendout ("$par,\$time$idm$otherargs");
-    for $par (3 .. $#params) {
-	my $p = $params[$par];
+    for my $parn (3 .. $#params) {
+	my $p = $params[$parn];
 	sendout (", $p");
 	print "MESSAGE $char, Parameter $p\n" if ($Debug);
     }
@@ -625,10 +628,10 @@ sub bitwidth {
 sub vpm_db_read_file {
     # Read when the unprocessed files were last known to not need processing
     my $filename = shift;
-    open (PWDFILE,"< $filename")	|| return;  # no error if fails
-    while (<PWDFILE>) {
-	chomp $_;
-	my ($tt_cmd, $tt_file, $tt_mtime) = split(/\t/);
+    my $fh = IO::File->new("<$filename") or return;  # no error if fails
+    while (my $line = $fh->getline) {
+	chomp $line;
+	my ($tt_cmd, $tt_file, $tt_mtime) = split(/\t/,$line);
 	$tt_cmd .= "";	# Warning removal
 	if ($tt_cmd eq "switch") {
 	    if ($tt_file =~ /vericov/) {
@@ -642,19 +645,19 @@ sub vpm_db_read_file {
 	    $File_Mtime_Read_Used{$tt_file} = 0;
 	}
     }
-    close PWDFILE;
+    $fh->close;
 }
 
 sub vpm_db_write_file {
     # Save which unprocessed files did not need processing
     my $filename = shift;
-    open (PWDFILE,"> $filename")	|| die("%Error: Can't write $filename.");
-    print PWDFILE "switch\tvericov\n" if $Opt_Vericov;
-    print PWDFILE "switch\tchiponly\n" if $Opt_Chiponly;
+    my $fh = IO::File->new(">$filename") or die "%Error: $! $filename.\n";
+    $fh->print ("switch\tvericov\n") if $Opt_Vericov;
+    $fh->print ("switch\tchiponly\n") if $Opt_Chiponly;
     foreach my $file (sort (keys %File_Mtime)) {
-	print PWDFILE "unproc\t$file\t$File_Mtime{$file}\n";
+	$fh->print ("unproc\t$file\t$File_Mtime{$file}\n");
     }
-    close PWDFILE;
+    $fh->close;
 }
 
 
@@ -793,7 +796,7 @@ sub vpm_process_one {
 ######################################################################
 # Parser functions called by Verilog::Parser
 
-package Verilog::Vpm::Parser;
+package Verilog::Vpm::Parser; ## no critic
 require Exporter;
 use Verilog::Parser;
 use base qw(Verilog::Parser);