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Commit a06b6dda authored by Wilson Snyder's avatar Wilson Snyder
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Verilog-Perl: fix vrename

git-svn-id: file://localhost/svn/Verilog-Perl/trunk/Verilog-Perl@41490 c99bdd1b-02e9-0310-b855-c9df8d5cb90a
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...@@ -3,6 +3,10 @@ Revision history for Perl extension Verilog::Language. ...@@ -3,6 +3,10 @@ Revision history for Perl extension Verilog::Language.
The contributors that suggested a given feature are shown in []. [by ...] The contributors that suggested a given feature are shown in []. [by ...]
indicates the contributor was also the author of the fix; Thanks! indicates the contributor was also the author of the fix; Thanks!
* Verilog::Language 3.00***
**** Fix vrename breakage in 3.00* releases. [David Price]
* Verilog::Language 3.001 2007/06/20 * Verilog::Language 3.001 2007/06/20
**** Support V2K function/task argument lists. **** Support V2K function/task argument lists.
......
...@@ -67,6 +67,7 @@ t/42_dumpcheck_2v.out ...@@ -67,6 +67,7 @@ t/42_dumpcheck_2v.out
t/42_dumpcheck_v2k.out t/42_dumpcheck_v2k.out
t/44_create.t t/44_create.t
t/46_link.t t/46_link.t
t/50_vrename.out
t/50_vrename.t t/50_vrename.t
t/60_vpm.t t/60_vpm.t
t/80_vppp.t t/80_vppp.t
......
# Generated by vrename on Thu Jul 5 09:01:51 2007
#
# Files read for this analysis:
vfile "verilog/test.v"
#
# Original Signal Name Name to change to
# -------------------- -----------------
#
sigren "a" "a" #verilog/test.v
sigren "b" "b" #verilog/test.v
sigren "example" "example" #verilog/test.v
sigren "result" "result" #verilog/test.v
sigren "z" "z" #verilog/test.v
#
# Use M-x compile in emacs to automatically perform the changes:
## Local Variables: ***
## compile-command: "./vrename -change verilog/test.v " ***
## End: ***
...@@ -13,22 +13,31 @@ BEGIN { plan tests => 6 } ...@@ -13,22 +13,31 @@ BEGIN { plan tests => 6 }
BEGIN { require "t/test_utils.pl"; } BEGIN { require "t/test_utils.pl"; }
print "Checking vrename...\n"; print "Checking vrename...\n";
{
# -List
my $changefile = "test_dir/signals.vrename";
unlink $changefile;
run_system ("${PERL} ./vrename -changefile=$changefile -list -xref verilog/test.v");
ok(1);
ok(files_identical($changefile, "t/50_vrename.out"));
unlink $changefile;
}
{
# Try renaming
mkdir 'test_dir/verilog', 0777;
run_system ("${PERL} ./vrename -change --changefile verilog/test.vrename"
." -o test_dir verilog/test.v");
ok(1);
ok(-r 'test_dir/verilog/test.v');
}
unlink 'signals.vrename'; {
run_system ("${PERL} ./vrename -list -xref verilog/test.v"); # Crypt
ok(1); my $changefile = "test_dir/signals.vrename";
ok(-r 'signals.vrename'); run_system ("${PERL} ./vrename -changefile=$changefile -list --crypt"
." -o test_dir verilog/test.v");
mkdir 'test_dir/verilog', 0777; run_system ("${PERL} ./vrename -changefile=$changefile -change --crypt"
run_system ("${PERL} ./vrename -change --changefile verilog/test.vrename" ." -o test_dir verilog/test.v");
." -o test_dir verilog/test.v"); ok(1);
ok(1); ok(-r 'test_dir/verilog/test.v');
ok(-r 'test_dir/verilog/test.v'); }
unlink 'signals.vrename';
run_system ("${PERL} ./vrename -list --crypt"
." -o test_dir verilog/test.v");
run_system ("${PERL} ./vrename -change --crypt"
." -o test_dir verilog/test.v");
ok(1);
ok(-r 'test_dir/verilog/test.v');
...@@ -40,6 +40,7 @@ sub files_identical { ...@@ -40,6 +40,7 @@ sub files_identical {
my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl); my $nl = $#l1; $nl = $#l2 if ($#l2 > $nl);
for (my $l=0; $l<=$nl; $l++) { for (my $l=0; $l<=$nl; $l++) {
if (($l1[$l]||"") ne ($l2[$l]||"")) { if (($l1[$l]||"") ne ($l2[$l]||"")) {
next if $l1[$l] =~ /Generated by vrename on/;
warn ("%Warning: Line ".($l+1)." mismatches; $fn1 != $fn2\n" warn ("%Warning: Line ".($l+1)." mismatches; $fn1 != $fn2\n"
."F1: ".($l1[$l]||"*EOF*\n") ."F1: ".($l1[$l]||"*EOF*\n")
."F2: ".($l2[$l]||"*EOF*\n")); ."F2: ".($l2[$l]||"*EOF*\n"));
......
...@@ -152,6 +152,7 @@ sub version { ...@@ -152,6 +152,7 @@ sub version {
sub debug { sub debug {
$Debug = 1; $Debug = 1;
$Verilog::Parser::Debug = $Debug; $Verilog::Parser::Debug = $Debug;
$Verilog::Vrename::Reader::Debug = $Debug;
} }
sub parameter { sub parameter {
...@@ -485,41 +486,38 @@ sub verilog_change_sig { ...@@ -485,41 +486,38 @@ sub verilog_change_sig {
###################################################################### ######################################################################
package Verilog::Vrename::Reader; package Verilog::Vrename::Reader;
require Exporter;
use strict;
use Carp; use Carp;
use vars qw( $Debug @ISA @EXPORT
$Last_Keyword $Last_Filename
%Modules_Sigs );
use Verilog::Parser; use Verilog::Parser;
use base qw(Verilog::Parser);
BEGIN { use vars qw($Debug);
@ISA = qw( Verilog::Parser ); use strict;
@EXPORT = qw( $Debug );
}
sub new { sub new {
my $class = shift; my $class = shift;
my $self = $class->SUPER::new(warning_limit=>1); my $self = $class->SUPER::new
(_last_keyword=>'',
_file_sigs=>{},
@_);
bless $self, $class; bless $self, $class;
return $self; return $self;
} }
sub _track_signal { sub _track_signal {
my $self = shift;
my $sig = shift; my $sig = shift;
$sig =~ s/\`//g; # Remove `s from define usages else won't match define declaration $sig =~ s/\`//g; # Remove `s from define usages else won't match define declaration
if (!$Modules_Sigs{$sig}) { if (!$self->{_file_sigs}{$sig}) {
push @{$main::Signal_Locs{$sig}}, $Last_Filename; push @{$main::Signal_Locs{$sig}}, $self->filename;
} }
$Modules_Sigs{$sig} = 1; $self->{_file_sigs}{$sig} = 1;
if ($main::Opt_Crypt && ($Last_Keyword eq "module" if ($main::Opt_Crypt && ($self->{_last_keyword} eq "module"
|| $Last_Keyword eq "function" || $self->{_last_keyword} eq "function"
|| $Last_Keyword eq "task")) { || $self->{_last_keyword} eq "task")) {
$main::Dont_Decrypt{$sig} = 1; $main::Dont_Decrypt{$sig} = 1;
$Last_Keyword = ""; $self->{_last_keyword} = "";
} }
} }
...@@ -528,9 +526,9 @@ sub keyword { ...@@ -528,9 +526,9 @@ sub keyword {
my $self = shift; # Parser invoked my $self = shift; # Parser invoked
my $token = shift; # What token was parsed my $token = shift; # What token was parsed
$Last_Keyword = $token; $self->{_last_keyword} = $token;
if ($main::Opt_Keywords) { if ($main::Opt_Keywords) {
_track_signal($token); $self->_track_signal($token);
} }
} }
...@@ -540,36 +538,30 @@ sub symbol { ...@@ -540,36 +538,30 @@ sub symbol {
my $sig = shift; # What token was parsed my $sig = shift; # What token was parsed
#print "Signal callback $self $token\n" if ($Debug); #print "Signal callback $self $token\n" if ($Debug);
_track_signal($sig); $self->_track_signal($sig);
} }
sub parse_file { sub parse_file {
# Read all signals in this filename # Read all signals in this filename
# Overloads Verilog::Parse::parse_file
@_ == 2 or croak 'usage: $parser->parse_file($filename)'; @_ == 2 or croak 'usage: $parser->parse_file($filename)';
my $self = shift; my $self = shift;
my $filename = shift; my $filename = shift;
local %Modules_Sigs = (); # Signals already found in module $self->{_file_sigs} = {}; # Signals already found in module
local $Last_Keyword = ""; $self->{_last_keyword} = "";
local $Last_Filename = $filename;
my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n";
while (my $line = $fh->getline() ) { $self->SUPER::parse_file($filename);
Verilog::Parser::parse ($self, $line);
}
if ($main::Opt_Crypt) { if ($main::Opt_Crypt) {
seek ($fh, 0, 0); my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n";
local $/ = undef; local $/ = undef;
my $filestrg = <$fh>; my $filestrg = <$fh>;
# Same test below # Same test below
if ($filestrg =~ /ENCRYPT_ME/) { if ($filestrg =~ /ENCRYPT_ME/) {
$main::Encrypt{$filename} = 1; $main::Encrypt{$filename} = 1;
} }
$fh->close;
} }
$fh->close;
} }
###################################################################### ######################################################################
......
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