Fix nettype declarations, msg2931.

Changes

@@ -4,6 +4,10 @@ The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
 
+* Verilog::Language 3.461 devel
+
+***	Fix nettype declarations, msg2931.  [Andreas Sunardi]
+
 * Verilog::Language 3.460 2019-01-26
 
 ***	Fix Verilog::Std being empty on fork, bug1394. [Corey Teffetalor]

Parser/VParseBison.y

@@ -1746,10 +1746,13 @@ data_declarationVarFrontClass:	// IEEE: part of data_declaration (for class_prop
 	;
 
 net_type_declaration:		// IEEE: net_type_declaration
-		yNETTYPE data_type idAny/*net_type_identifier*/ ';' { }
+		yNETTYPE data_type idAny/*net_type_identifier*/ ';'
+							{ PARSEP->syms().replaceInsert(VAstType::TYPE, $3); }
 	//			// package_scope part of data_type
-	|	yNETTYPE data_type idAny yWITH__ETC package_scopeIdFollows id/*tf_identifier*/ ';' { }
-	|	yNETTYPE package_scopeIdFollows id/*net_type_identifier*/ idAny/*net_type_identifier*/ ';' { }
+	|	yNETTYPE data_type idAny yWITH__ETC package_scopeIdFollowsE id/*tf_identifier*/ ';'
+							{ PARSEP->syms().replaceInsert(VAstType::TYPE, $3); }
+	|	yNETTYPE package_scopeIdFollowsE id/*net_type_identifier*/ idAny/*net_type_identifier*/ ';'
+							{ PARSEP->syms().replaceInsert(VAstType::TYPE, $4); }
 	;
 
 constE<str>:			// IEEE: part of data_declaration

t/35_sigparser.out

@@ -538,6 +538,11 @@ verilog/parser_bugs.v:567: VAR  'parameter' 'B' 'module' '' '' '' '8
                 'b
                 1'
 verilog/parser_bugs.v:572: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:574: MODULE  'module' 'msg2931' undef '0'
+verilog/parser_bugs.v:576: VAR  'var' 'mynet1' 'module' '' 'net1_t' '' ''
+verilog/parser_bugs.v:578: VAR  'var' 'mynet2' 'module' '' 'net2_t' '' ''
+verilog/parser_bugs.v:580: VAR  'var' 'mynet3' 'module' '' 'net3_t' '' ''
+verilog/parser_bugs.v:581: ENDMODULE  'endmodule'
 verilog/pinorder.v:001: COMMENT  '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package'
 verilog/pinorder.v:002: COMMENT  '//'
 verilog/pinorder.v:003: COMMENT  '// This file ONLY is placed into the Public Domain, for any use,'

t/35_sigparser_ps.out

@@ -566,6 +566,11 @@ verilog/parser_bugs.v:567: VAR  'parameter' 'B' 'module' '' '' '' '8
                 'b
                 1'
 verilog/parser_bugs.v:572: ENDMODULE  'endmodule'
+verilog/parser_bugs.v:574: MODULE  'module' 'msg2931' undef '0'
+verilog/parser_bugs.v:576: VAR  'var' 'mynet1' 'module' '' 'net1_t' '' ''
+verilog/parser_bugs.v:578: VAR  'var' 'mynet2' 'module' '' 'net2_t' '' ''
+verilog/parser_bugs.v:580: VAR  'var' 'mynet3' 'module' '' 'net3_t' '' ''
+verilog/parser_bugs.v:581: ENDMODULE  'endmodule'
 verilog/pinorder.v:001: COMMENT  '// DESCRIPTION: Verilog-Perl: Example Verilog for testing package'
 verilog/pinorder.v:002: COMMENT  '//'
 verilog/pinorder.v:003: COMMENT  '// This file ONLY is placed into the Public Domain, for any use,'

verilog/parser_bugs.v

@@ -570,3 +570,12 @@ module bug1340;
                 1
 		;
 endmodule
+
+module msg2931;
+   nettype int net1_t;
+   net1_t mynet1;
+   nettype int net2_t with resolvefunc;
+   net2_t mynet2;
+   nettype net_t net3_t;
+   net3_t mynet3;
+endmodule