Put root localparams into module, bug471.

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilog::Language 3.31*** devel
 
+***	Put root localparams into $root module, bug471. [Corey Teffetalor]
+
 ****	Fix comment callback starting line, bug459. [Max Bjurling]
 
 ****	Fix genvar and begin under generate, bug461.  [Alex Solomatnikov]

Netlist.pm

@@ -139,6 +139,15 @@ sub new_module {
     return $modref;
 }
 
+sub new_root_module {
+    my $self = shift;
+    $self->{_modules}{'$root'} ||=
+	$self->new_module(keyword=>'root_module',
+			  name=>'$root',
+			  @_);
+    return $self->{_modules}{'$root'};
+}
+
 sub defvalue_nowarn {
     my $self = shift;
     my $sym = shift;
@@ -581,6 +590,11 @@ be first, the top most module will be last.
 
 Creates a new Verilog::Netlist::Module.
 
+=item $netlist->new_root_module
+
+Creates a new Verilog::Netlist::Module for $root, if one doesn't already
+exist.
+
 =item $netlist->top_modules_sorted
 
 Returns name sorted list of Verilog::Netlist::Module, only for those

Netlist/File.pm

@@ -249,7 +249,7 @@ sub var {
     my $value = shift;
     print " Sig $name dt=$decl_type nt=$net_type d=$data_type\n" if $Verilog::Netlist::Debug;
 
-    return if !($objof eq 'module' || $objof eq 'interface' || $objof eq 'modport');
+    return if !($objof eq 'module' || $objof eq 'interface' || $objof eq 'modport' || $objof eq 'netlist');
 
     my $msb;
     my $lsb;
@@ -260,6 +260,10 @@ sub var {
     }
 
     my $underref = $self->{_modportref} || $self->{modref};
+    if ($objof eq 'netlist') {
+	$underref = $self->{netlist}->new_root_module
+	    (filename=>$self->filename, lineno=>$self->lineno);
+    }
     if (!$underref) {
 	return $self->error ("Signal declaration outside of module definition", $name);
     }

t/40_netlist.t

@@ -8,7 +8,7 @@
 use strict;
 use Test::More;
 
-BEGIN { plan tests => 25 }
+BEGIN { plan tests => 19 }
 BEGIN { require "t/test_utils.pl"; }
 
 #$Verilog::Netlist::Debug = 1;
@@ -46,13 +46,14 @@ is($nl->find_module("v_hier_sub")->level, 2);
 is($nl->find_module("v_hier_subsub")->level, 1);
 
 my @mods = map {$_->name} $nl->modules_sorted_level;
-is ($mods[0], 'v_hier_noport');
-is ($mods[1], 'v_hier_subsub');
-is ($mods[2], 'v_sv_pgm');
-is ($mods[3], 'v_hier_sub');
-is ($mods[4], 'v_hier_top2');
-is ($mods[5], 'v_hier_top');
-is ($mods[6], 'v_sv_mod');
+is_deeply (\@mods, ['$root',
+		    'v_hier_noport',
+		    'v_hier_subsub',
+		    'v_sv_pgm',
+		    'v_hier_sub',
+		    'v_hier_top2',
+		    'v_hier_top',
+		    'v_sv_mod']);
 
 # Width checks
 {

t/42_dumpcheck_1.out

+Module:$root  Kwd:root_module  File:verilog/v_hier_top.v
+  Net:GLOBAL_PARAM    DeclT:localparam  NetT:  DataT:  Array:  Value:1
 Module:v_comments  Kwd:module  File:verilog/v_comments.v
   Port:a  Dir:in  DataT:  Array:
   Port:b  Dir:inout  DataT:[10:0]  Array:

verilog/v_hier_top.v

@@ -37,6 +37,8 @@ module v_hier_top (/*AUTOARG*/
 
 endmodule
 
+localparam  GLOBAL_PARAM = 1;
+
 // Local Variables:
 // eval:(verilog-read-defines)
 // End: