Fix c style var array declarations.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***	Add vhier --forest and --instance.  [by John Busco]
 
+****	Fix c style var array declarations. [by Jack Cummings]
+
 
 * Verilog::Language 3.313 2012/12/14
 

Parser/VParseBison.y

@@ -1804,7 +1804,7 @@ netSigList:			// IEEE: list_of_port_identifiers
 netSig:				// IEEE: net_decl_assignment -  one element from list_of_port_identifiers
 		netId sigAttrListE			{ VARDONE($<fl>1, $1, "", ""); }
 	|	netId sigAttrListE '=' expr		{ VARDONE($<fl>1, $1, "", $4); }
-	|	netId rangeList sigAttrListE		{ VARDONE($<fl>1, $1, $2, ""); }
+	|	netId variable_dimension sigAttrListE		{ VARDONE($<fl>1, $1, $2, ""); }
 	;
 
 netId<str>:

t/35_sigparser.out

@@ -503,7 +503,7 @@ verilog/parser_sv.v:011: INTERFACE  'interface' 'itf'
 verilog/parser_sv.v:011: VAR  'parameter' 'num_of_cli' 'interface' '' '' '' '0'
 verilog/parser_sv.v:012: VAR  'var' 'blabla' 'interface' '' 'logic' '' ''
 verilog/parser_sv.v:013: VAR  'var' 'addr' 'interface' '' 'logic [7:0]' '' ''
-verilog/parser_sv.v:013: VAR  'var' 'data' 'interface' '' 'logic [7:0]' '' ''
+verilog/parser_sv.v:013: VAR  'var' 'data' 'interface' '' 'logic [7:0]' '[9]' ''
 verilog/parser_sv.v:014: MODPORT  'modport' 'Master'
 verilog/parser_sv.v:014: VAR  'port' 'data' 'modport' '' '' '' 'data'
 verilog/parser_sv.v:014: PORT  'data' 'modport' 'input' '' '' '1'
@@ -533,6 +533,7 @@ verilog/parser_sv.v:022: PORT  'd_out' 'module' 'output' 'logic' '' '6'
 verilog/parser_sv.v:025: IMPORT  'mypackage' '*'
 verilog/parser_sv.v:027: VAR  'var' 'd_int' 'module' '' 'logic' '' ''
 verilog/parser_sv.v:028: VAR  'var' 'data_' 'module' '' 'logic [7:0]' '' ''
+verilog/parser_sv.v:028: VAR  'var' 'bork' 'module' '' 'logic [7:0]' '[2]' ''
 verilog/parser_sv.v:029: CONTASSIGN  'assign' 'd_int' 'd_in+pkg_data'
 verilog/parser_sv.v:031: CONTASSIGN  'assign' 'modported_int.data' 'data_'
 verilog/parser_sv.v:046: ENDMODULE  'endmodule'

verilog/parser_sv.v

@@ -10,7 +10,7 @@ endmodule : times
 
 interface itf #(parameter num_of_cli = 0);
    logic blabla;
-   logic [7:0] addr, data;
+   logic [7:0] addr, data[9];
    modport Master(input data, date_delayed, output addr);
 endinterface : itf
 
@@ -25,7 +25,7 @@ module test (
    import mypackage::*;
 
    logic 	d_int;
-   logic [7:0] 	data_;
+   logic [7:0] 	data_, bork[2];
    assign      d_int = d_in + pkg_data;
 
    assign  modported_int.data = data_;